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pnx8510; pnx8511 analog companion chip rev. 04 ? 12 january 2004 product data 1. general description the pnx8510; pnx8511 is an analog backend companion chip to digital ics processing video and audio signals. the primary difference between the pnx8510 and the pnx8511 is: ? pnx8510 includes the macrovision? pay-per-view copy protection system ? pnx8511 does not include macrovision? pnx8510/11 provides two video encoders through two standardized d1 interfaces. the encoders can be bypassed to get dire ct access to the video dacs for higher resolution displays. pnx8510/11 also contains a sophisticated sync raster engine which can be utilized to generate various syn chronization patterns for interlaced and non-interlaced image formats. the sync ra ster engine together with an up-sampling filter and a sync insertion unit compose a complete hdtv-capable data path including tri-level sync generation. pnx8510/11 also provides two independent pa irs of stereo audio dacs with two corresponding i 2 s-bus interfaces. figure 1 shows the pnx8510/11 with a typical source decoder. 2. features 2.1 pnx8510 six 10-bit video dacs running at up to 135 mhz 1lsb dnl four audio dacs arranged as two stereo pairs two built-in digital video encoders pal b/g, ntsc-m and secam encoding two 10-bit d1 inputs with embedded vbi data tw o i 2 s-bus independent audio input ports i 2 c-bus programmable (slave interface) support for high resolution video out up to 81 mhz interface clock rate support for input modes 2xd1, rgb, 1x 2d1 muxed, 24/30-bit rgb, dd1 programmable generation of embedded analog and external digital sync signals compliant to vesa and smpte 274 standards vbi encoding for standard definition video out
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 2 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. teletext insertion for pal-wst, ntsc-wst, nabts vps video programming service encoding closed caption encoding cgms copy generation management system according to cpr-1204 internal color bar generator for standard definition video out jtag-controlled test signals on video and audio converters macrovision? pay-per-view copy protection system, rev. 7.1 (scart support with macrovision? copy protection on the rgb lines) 2.2 pnx8511 pnx8511 has all the features of pnx8 510 with the exception of macrovision? 3. applications digital television set-top box multimedia applications 4. ordering information 5. block diagram table 1: ordering information type number package name description version pnx8510hw/b1 htqfp100 plastic thermal enhanced thin quad flat package; 100 leads, body 14 x 14 x 1 mm, exposed die pad sot638-1 pnx8511hw/b1 htqfp100 plastic thermal enhanced thin quad flat package; 100 leads, body 14 x 14 x 1 mm, exposed die pad sot638-1 fig 1. system level diagram mdb636 10 10 i 2 s-bus i 2 s-bus i 2 c-bus 3 2 2 5 pnx8510/11 source decoder ic rgb or y/c y cvbs c (cvbs) a1 r/l a2 r/l gpio hsync vsync dv1_out dv2_out a1 out a2 out i 2 c hsync vsync blank
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 3 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. pinning information 6.1 pin description fig 2. pin configuration pnx8510hw/b1 pnx8511hw/b1 v dd(adac) dv4_in2 v ss(adac) dv5_in2 jtag_rst dv6_in2 reset_n dv7_in2 v ss(aud) dv8_in2 v ss(aud) dv9_in2 v ddd(adac) dv_clk2 v ss v dd test1 v ss test2 dv0_in1 test3 dv1_in1 test4 dv2_in1 v ss dv3_in1 v dd dv4_in1 i2s_in1_sck dv_clk1 i2s_in1_ws v dd i2s_in1_sd v ss i2s_aos1_clk v ssa(vdac) v ss i2s_in2_sck i2s_in2_ws i2s_in2_sd v ss i2s_aos2_clk n.c. dv5_in1 dv6_in1 dv7_in1 dv8_in1 dv9_in1 v dd rset_dac1 i2c_sda aout_l1 i2c_scl v ss1(adac) vsync_in v ddo1(adac) hsync_in v ref1(aud) blank_in aout_r1 v ss aout_l2 vsync_out v ddo2(adac) hsync_out v ref2(aud) v dd v ss2(adac) v ss aout_r2 v dd v dd2(adac) v dda(vdac) v sso2(adac) vout5 gpio5 irtn2 gpio4 v dda(vdac) v dd vout4 v ss vout3 dv0_in2 irtn1 dv1_in2 vout2 vout6 reset2 v ssa(vdac) v dda(vdac) vout1 dv2_in2 gpio3 gpio2 gpio1 v dd v ss v dda(vdac) dv3_in2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 56 55 54 53 52 51 15 16 17 18 19 61 60 59 58 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 81 80 79 78 77 76 40 41 42 43 44 86 85 84 83 82 mdb793 table 2: pin description symbol pin type description v dd(adac) 1 - audio dac analog supply v ss(adac) 2 - audio dac analog ground jtag_rst 3 - jtag reset reset_n 4 - chip reset in signal (low active) v ss(aud) 5 - audio digital ground v ss(aud) 6 - audio digital ground v ddd(adac) 7 - audio dac digital supply v ss 8 - digital ground test1 9 i jtag controller test data input test2 10 o jtag controller test data output
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 4 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. test3 11 i jtag controller test clock input test4 12 i jtag controller test mode select input v ss 13 - digital ground v dd 14 - digital supply i2s_in2_sck 15 i/o bit clock io for secondary audio channel i2s_in2_ws 16 i/o word select io for secondary audio channel i2s_in2_sd 17 i serial data in for secondary audio channel v ss 18 - digital ground i2s_aos2_clk 19 i oversampling clock input for secondary audio channel i2s_in1_sck 20 i/o bit clock io for primary audio channel i2s_in1_ws 21 i/o word select io for primary audio channel i2s_in1_sd 22 i serial data in for primary audio channel i2s_aos1_clk 23 i oversampling clock input for primary audio channel v ss 24 - digital ground v dd 25 - digital supply i2c_sda 26 i/o i 2 c data line (bi-directional) i2c_scl 27 i i 2 c clock line (input) vsync_in 28 i vertical sync input for primary video interface hsync_in 29 i horizontal sync input for primary video interface blank_in 30 i blanking input signal for primary video pipeline v ss 31 - digital ground vsync_out 32 o vertical sync output for primary video pipeline hsync_out 33 o horizontal sync output for primary video pipeline v dd 34 - digital supply v ss 35 - digital ground v dd 36 - digital supply v dda(vdac) 37 - analog supply for video dacs vout5 38 o video output for secondary channel, y/cvbs-dac irtn2 39 - current return path fo r c-dac and cvbs/y-dac vout6 40 o video output for secondary channel, c-dac reset2 41 - current setting resistor for secondary channel dacs v ssa(vdac) 42 - analog ground for video dacs v dda(vdac) 43 - analog supply for video dacs vout1 44 o video output for primary video dac 1 (cvbs/y) v dda(vdac) 45 - analog supply for video dacs vout4 46 o video output for primary video dac 4 (blue) vout3 47 o video output for primary video dac 3 (y/green) irtn1 48 - current return path for all primary channel dacs vout2 49 o video output for primary video dac 2 (c/red) v dda(vdac) 50 - analog supply for video dacs rset_dac1 51 - current setting resistor for primary channel dacs table 2: pin description ?continued symbol pin type description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 5 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. n.c. 52 - no connection (leave floating) v ssa(vdac) 53 - analog ground for video dacs v ss 54 - digital ground v dd 55 - digital supply dv_clk1 56 - primary video interface clock dv9_in1 57 i primary video d1 input dv8_in1 58 i primary video d1 input dv7_in1 59 i primary video d1 input dv6_in1 60 i primary video d1 input dv5_in1 61 i primary video d1 input dv4_in1 62 i primary video d1 input dv3_in1 63 i primary video d1 input dv2_in1 64 i primary video d1 input dv1_in1 65 i primary video d1 input dv0_in1 66 i primary video d1 input v ss 67 - digital ground v dd 68 - digital supply dv_clk2 69 - secondary video interface clock dv9_in2 70 i secondary video d1 input dv8_in2 71 i secondary video d1 input dv7_in2 72 i secondary video d1 input dv6_in2 73 i secondary video d1 input dv5_in2 74 i secondary video d1 input dv4_in2 75 i secondary video d1 input dv3_in2 76 i secondary video d1 input dv2_in2 77 i secondary video d1 input dv1_in2 78 i secondary video d1 input dv0_in2 79 i secondary video d1 input v ss 80 - digital ground v dd 81 - digital supply v ss 82 - digital ground v dd 83 - digital supply gpio1 84 i/o general purpose input/output gpio2 85 i/o general purpose input/output gpio3 86 i/o general purpose input/output gpio4 87 i/o general purpose input/output gpio5 88 i/o general purpose input/output v ss02(adac) 89 - audio dac output buffer supply v dd2(adac) 90 - audio dac supply aout_r2 91 o audio output for right secondary audio channel v ss2(adac) 92 - audio dac ground table 2: pin description ?continued symbol pin type description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 6 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. functional description 7.1 video pipeline the video pipeline contains two independent video channels. the primary channel is used to display graphic or video content on a standard television, crt monitor or an hdtv system. the secondary video channel may connect to a vcr or a second standard tv for recording or secondary display purposes. no high definition or rgb output is available through the second video channel. the two video pipelines are driven by two standard d1 interfaces, which can operate in various modes in 8 or 10-bit precision. the video modes are described below . 7.1.1 video modes the video interfaces and sync raster engines are designed in a generic way. the only limiting factor is the data rate of the rece ived video streams. all formats with a total interface speed requirement below 81 mhz can be displayed by the pnx8510/11 . v ref2(aud) 93 - audio dac reference v dd02(adac) 94 - audio dac output buffer supply aout_l2 95 o audio output for left secondary audio channel aout_r1 96 o audio output for right primary audio channel v ref1(aud) 97 - audio dac reference v ddo1(adac) 98 - audio dac output buffer supply v ss1(adac) 99 - audio dac ground aout_l1 100 o audio output for left primary audio channel table 2: pin description ?continued symbol pin type description fig 3. video path block diagram mdb637 rgb bypass secondary denc primary denc ccir656-demux vbi-extract de-interleave r/v/c-dac g/y-dac b/u-dac y/cvbs-dac y/cvbs-dac c-dac vout2 vout3 vout4 vout1 vout5 vout6 table 3: primary video channel standard interface modes interface modes mode interface speed 4:4:4 rgb or yuv or ycrcb or yprpb 4:4:4 muxed components 10/8-bit up to 81 mhz 4:2:2 yuv or ycrcb or yprpb 4:2:2 muxed components 10/8-bit up to 81 mhz
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 7 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 4: primary video channel standard display modes display modes mode interface speed used data path pal/ntsc/secam 4:2:2 yuv i.e. pal: 864 pixel/line x 312.5 lines/field x 50hz = 13.5 mhz/y samples 6.75 mhz/u samples 6.75 mhz/v samples 4:2:2 muxed components 10/8-bit 27 mhz sd-cvbs-data path pal/ntsc/secam rgb/yuv i.e. pal: 864 pixel/line x 312.5 lines/field x 50 hz = 13.5 mhz/y samples 6.75 mhz/u samples 6.75 mhz/v samples 4:2:2 muxed components 10/8-bit 27 mhz sd-cvbs and rgb/yuv data paths 2fh pal/ntsc/secam 4:4:4 rgb/yuv/ycrcb/yprpb i.e. pal: 864 pixel/line x 312.5 lines/field x 50 hz x2 = 27 mhz/component 4:4:4 muxed components 10/8-bit 81 mhz hd-data path 480p pal/ntsc/secam 4:4:4 rgb/yuv/ycrcb/yprpb i.e. pal: 864 pixel/line x 625 lines/field x 50 hz = 27 mhz/component 4:4:4 muxed components 10/8-bit 81 mhz hd-data path generic d1 mode; the interface clock can run up to 81 mhz, the components can have either 4:2:2 or 4:4:4 color resolution, but must be in the correct color space. 4:4:4 muxed components/ 4:2:2 muxed components (use of both d1 interfaces required) 10/8-bit up to 81 mhz hd-data path table 5: secondary video channel standard interface modes interface modes mode interface speed 4:2:2 yuv or ycrcb or yprpb 4:2:2 muxed components 10/8-bit 27 mhz
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 8 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] in case of the 24/30-bit full parallel input, no secondary audio channel is available. table 6: 24/30-bit rgb/yuv mode both d1 interfaces and the secondary audio channel are combined to provide high-speed direct access to video dacs display/interface mode mode interface speed pin assignment 24-bit mode pin assignment 30-bit mode 24/30-bit rgb/yuv [1] 24-bit direct rgb/yuv 8/10-bit up to 81 mhz red[7] - i 2 s_in2_sd red[9] - i 2 s_in2_sd red[6] - i 2 s_in2_ws red[8] - i 2 s_in2_ws red[5] - i 2 s_in2_sck red[7] - i 2 s_in2_sck red[4] - i 2 s_aos2_clk red[6] - i 2 s_aos2_clk red[3] - dv_in1[9] red[5] - dv_in1[9] red[2] - dv_in1[8] red[4] - dv_in1[8] red[1] - dv_in1[7] red[3] - dv_in1[7] red[0] - dv_in1[6] red[2] - dv_in1[6] red[1] - gpio[5] green[7] - dv_in1[5] red[0] - gpio[4] green[6] - dv_in1[4] green[5] - dv_in1[3] green[9] - dv_in1[5] green[4] - dv_in1[2] green[8] - dv_in1[4] green[3] - dv_in1[1] green[7] - dv_in1[3] green[2] - dv_in1[0] green[6] - dv_in1[2] green[1] - dv_in2[9] green[5] - dv_in1[1] green[0] - dv_in2[8] green[4] - dv_in1[0] green[3] - dv_in2[9] blue[7] - dv_in2[7] green[2] - dv_in2[8] blue[6] - dv_in2[6] green[1] - gpio[3] blue[5] - dv_in2[5] green[0] - gpio[2] blue[4] - dv_in2[4] blue[3] - dv_in2[3] blue[9] - dv_in2[7] blue[2] - dv_in2[2] blue[8] - dv_in2[6] blue[1] - dv_in2[1] blue[7] - dv_in2[5] blue[0] - dv_in2[0] blue[6] - dv_in2[4] blue[5] - dv_in2[3] blue[4] - dv_in2[2] blue[3] - dv_in2[1] blue[2] - dv_in2[0] blue[1] - gpio[1] blue[0] - dv_clk2
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 9 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] in case of the combined double d1 mode, no secondary display channel is available the pnx8510/11 supports color space conversion only in the primary rgb standard definition data path. for the high definition part of the primary video data path and for the secondary video data path no color space conversion is available. hence the video data has to be provided in the display destination color space. aside from built-in video encoders, which generate all necessary timing and filtering for an appropriate sync raster for pal, ntsc and secam, the pnx8510/11 contains a separate raster-generation engine which also supports but is not limited to the hd-formats, such as the smpte 274m. the pnx8510/11 also contains an up-sampling filter to convert 4:2:2 formats (other than standard definition formats) to 4:4:4. in the case of combined double d1 mode, no secondary display channel is available. table 7: single interface mode 2 (d1) display/interface mode mode interface speed single interface mode 2 (d1) accommodates 2 synchronous multiplexed d1 streams for low cost applications (b oth streams are extracted). 2x muxed 4:2:2 single d1 8/10-bit 54 mhz table 8: interleaved interface mode display/interface mode mode interface speed interleaved interface mode same formats as in single interface mode 1 and 2 but only one of the two interleaved video streams is extracted per interface. selection of the extracted slice is possible by software, usage of two pnx8510/11 chips possible to support up to 4 display/record devices 2x muxed 4:2:2 single d1 or 2x muxed 4:4:4 rgb/yuv 8/10-bit 54 mhz or 81 mhz or pos-neg edge 27 mhz (saa7128 compliant) table 9: combined double d1 mode display/interface mode mode interface speed combined double d1 mode: [1] the two d1 interfaces are combined to carry a single hdtv stream in 4:2:2 yuv or 4:2:2 yprpb format primary d1: y channel secondary d1: muxed uv or prpb channel i.e.: 1920x1080 60 hz interlaced 2200 pixel/line x 562.5 lines/field x 60 hz = 74.25 mhz/y samples 37.125 mhz/cr/pr samples 37.125 mhz/cb/pb samples 2 combined d1 8/10-bit up to 81 mhz per d1
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 10 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. if the interface is operated in d1 mode, the data stream presented to the interface has to be d1 compliant i.e., the maximum and minimum codes (8-bit 0x00 0xff, 10-bit 0x000 0x3ff) must not occur during active video. a detailed description of video input data formats can be found in section 7.1.2 . the video modes listed correspond to the se ttings of the demux_mode bits in the register 0x95 vmuxctl section 8.1 . if the video interface clock frequency is not equivalent to the processing and the video dac operation frequency the appropriate divider registers in the audi o/clock register section have to be programmed. as a general rule the settings in ta b l e 10 should be used: 7.1.2 video input modes the pnx8510/11 video interface supports a wide variety of video formats. the video interface is designed in a generic fashion. it is de-coupled from the actual video data paths in the system and imposes only a few restrictions on the video data streams provided to the chip. this section explains the possible video stream formats and provides details on synchronizing the pnx8510/11 with respec t to a particular video data format. the pnx8510/11 accepts the video formats shown in figure 4 to figure 10 on a single interface with up to 81 mhz interface clock: yuv 4:2:2 this is the ccir-656 compliant format and will mainly be used at an interface speed of 27 mhz to feed the video encoder modules in the chip. this is the standard interface format for the secondary video encoder pipeline unless the chip is used in high definition (hd) mode. the yuv 4:2:2 format can also be used to feed the hd data path as long as the pixel clock rate stays below 81 mhz. to operate the hd da ta path with 4:2:2 source material the 4:2:2 to 4:4:4 filter should be enabled to achieve the best video quality. table 10: clock frequency settings mode interface clock processing clock dac clock 4:2:2 yuv sd single interface mode 27 mhz 27 mhz 27 mhz 4:4:4 rgb 2fh single interface mode 81 mhz 27 mhz 27 mhz 4:2:2 yuv 1080i double interface mode 74.25 mhz 74.25 mhz 74.25 mhz fig 4. yuv 4:2:2 mdb638 ff 00 00 eav 80 10 80 10 ff 00 00 sav u1 y1 v1 y2 u3 y3
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 11 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. rgb 4:4:4 this mode is only useful if the hd data path in the pnx8510/11 is in operation. the rgb 4:4:4 interface mode is not applicab le to the standard definition rgb path operation due to the implicit clocking requirements. the data rate for standard definition rgb 4:4:4 data would be 13.5 mhz per component result ing in an interface speed of 40.5 mhz. because the chip does not contai n any plls, it is not possible to extract 27 mhz out of the interface clock. yuv 4:4:4 this mode is useful only if the hd data path in the pnx8510/11 is in operation. yuv 4:2:2 interleaved this mode supports two video data streams through one physical video interface. it can be used to utilize both video encoder channels in the chip with one interface only or to hook up two pnx8510/11 devices to one source providing an interleaved data stream. each chip extracts one slice from the interleaved stream. this video format is useful for the encoder standard definition data path only. rgb 4:4:4 interleaved fig 5. rgb 4:4:4 fig 6. yuv 4:4:4 fig 7. yuv 4:2:2 interleaved fig 8. rgb 4:4:4 interleaved mdb639 ff 00 00 eav 80 10 80 10 ff 00 00 sav r1 g1 b1 r2 g2 b2 mdb640 ff 00 00 eav 80 10 80 10 ff 00 00 sav y1 u1 v1 y2 u2 v2 mdb641 ff ff 00 00 00 00 eav eav 80 80 10 10 u1 b y1 a y1 b v1 a v1 b y2 a y2 b 00 00 ff ff 00 00 sav sav u1 a mdb642 ff ff 00 00 00 00 eav eav 80 80 10 10 r1 b g1 a g1 b b1 a b1 b r2 a r2 b 00 00 ff ff 00 00 sav sav r1 a
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 12 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. this mode supports two video data streams through one physical video interface. it can be used to utilize both video encoder channels in the chip with one interface only or to hook up two pnx8510/11 devices to one source providing an interleaved data stream. each chip extracts one slice from the interleaved stream. this video format is useful for the standard definition rgb data path as well as for the hd data path. yuv 4:4:4 interleaved this mode supports two video data streams through one physical video interface. it can be used to utilize both vi deo encoder cha nnels with one interfac e only or to hook up two pnx8510/11 devices to one source providing an interleaved data stream. each chip extracts one slice from the interl eaved stream. this video format is useful for the hd data path only. there are two modes defined for interleaved data streams. one is to run the interface at twice the speed and provide a qualifier on the hsync input to qualify a certain slice. the qualifier is essentially the interface clock divided by two. the other interleaved interface format works on both clock edges of the interface clock, so one slice is latched at the positive edge and the other slice is latched at the negative edge of the interface clock. yuv 4:2:2 hd two-channel format this format is used only for high definit ion video modes that exceed interface clock requirements of 81 mhz. for this video interface mode, both physical interfaces of the chip are utilized. the primary interface gets a d1-like data stream, which only contains the luminance information, while the secondary d1 interface carries the chrominance information. 7.1.3 video input module the video input module is responsible for accommodating all supported video data formats. it delivers a de-multiplexed and de-sliced data stream to the video processing modules. as depicted in figure 11 , the ic has two video input ports which can accommodate 8 or 10-bit wide video data streams. fig 9. yuv 4:4:4 interleaved fig 10. yuv 4:2:2 hd two-channel format mdb643 ff ff 00 00 00 00 eav eav 80 80 10 10 y1 b u1 a u1 b v1 a v1 b y2 a y2 b 00 00 ff ff 00 00 sav sav y1 a mdb644 ff 00 00 eav 80 10 80 10 ff 00 00 sav y1 y2 y3 y4 u5 y6 ff 00 00 eav 80 10 80 10 ff 00 00 sav u1 v2 u3 v3 u5 v5
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 13 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. the normal mode of operation is that the dv 1 interface is routed to the primary video data paths and the dv2 interface is routed to the secondary video data paths. the ic however accepts also so called sliced data form ats. a sliced data format contains two single video data streams multiplexed together on a component basis. a more detailed description of the arrangement of the components can be found in section 7.1.2 . to enable sliced data formats the slice_mode bit of the register vmuxctl (register offset 0x95) has to be set. the de-slice module essentially takes the two data streams apart by simply two to one de-multiplexing. the routing of the resulting two video data streams is determined by setting the sel register bits in the primary and secondary video data path apertures appropriately. sliced data formats come in two different flavors: double edge and qualified. the double edge slice format has data changes on the positive and the negative clock edge where as the qualified mode qualifies one data stream of the two multiplexed ones with an active high on the hsync signal. to use this mode the use_qualifier bit in the register inpctl (offset 0x3a) must be set. the order of the slice qualification can be changed by setting the qual_invert bit of the same register (offset 0x3a). since each of the video input interfaces can accept sliced data formats a total of four video data streams could be routed into the ic and two of them can be selected to be forwarded to the primary and the secondary video display pipeline. the structure of the video input module is shown in figure 11 . fig 11. block diagram - video input module mdb645 rst sync primary rst sync secondary register array primary register array secondary out- sel out- sel de-slice vbi data slicer vbi data slicer de-slice output formatter demux_mode r/y/y g/u/u-v b/v y u - v output formatter sav-eav detection sav-eav detection demux_mode 8/10-bit mode data 1 input d1-in secondary sel1 sel2 ttx data port ttx data port slice_mode o_e o_e slice_dir slice_mode slice_dir 8/10-bit mode
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 14 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.1.4 video dac control the pnx8510/11 contains six video dacs, four dedicated to the primary video pipeline and two to the secondary video processing path. the first dac of the primary video channel (vout1) is always assigned to the primary standard definition data path. the output of the dac can be changed from cvbs to y by resetting the cvbsen bit of the register dacctrl (offset 0x2d) to zero. the second dac of the primary video channel (vout2) is assigned to either the standard definition (sd) data path or high definition (hd) data path. in the sd mode, it carries the chrominance, c (y/c operati on) if the cen bit in the dacctrl (offset 0x2d) is set or the red/v channel (rgb/c omponent mode operation) if the cen bit of the dacctrl (offset 0x2d) is reset. in hd mode (sd_hd bit of inpctl register, offset 0x3a is set to zero) this dac carr ies either the red channel or the y channel depending on whether the hd path is operat ed in rgb or yuv mode. note that the cen bit must be reset for hd operation. the third dac of the primary video channel (vout3) is also assigned to either the standard definition (sd) data path or high de finition (hd) data path. in sd mode, it carries the luminance channel if the vbsen bit in the dacctrl (offset 0x2d) is set or the green/y ch annel if the vbsen bit is reset (rgb/component mode operation). if the high definition data path is operational (sd_hd=1?b0) this dac carries the green or u channel depending on whether the hd path is operated in yuv or rgb mode. the configuration of the fourth dac in t he primary video data path (vout4) can not be changed with a programming register. this dac carries the blue or u channel in standard definition mode and the blue or v channel if the high definition data path is active. the configuration of the dacs for the sec ondary video data path is limited to the cvbs/y dac (vout5). if the cvbsen bit in the dacctrl register (offset 0x2d) is set, this dac carries the c vbs signal. resetting the bit re sults in the y signal being assigned to this dac. the second dac of the secondary video pipeline (vdac6) always carries the chrominance signal. 7.1.5 vbi data vbi data extraction from a d1 data stream is only supported for standard definition formats. the extraction follows the concep t of philips video decoders, such as the saa7114. both video interfaces can carry vbi data information. the content of the vbi data is entirely determined by the source decoder chip software driver. the pnx8510/11 supports two vbi data streams. the limitation to two vbi data streams implies certain limitations when using multiple pnx8 510/11 chips in a system. in this case one pnx8510/11 gets either one or two (all) vbi data streams. the other pnx8510/11 ic would get one or none. only the anc/sav-eav header style vbi data encoding mode is supported in the pnx8510/11. according to these standards vbi data is always inserted in the horizontal blanking interval of a line. the data is preceded by an anc header which is
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 15 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. programmable. an internal header following the anc contains a programmable sliced data identifier with the number of data byte s transmitted and two internal identification tokens containing data type, field type and line number. figure 12 illustrates how the data is encoded in the horizontal blanking interval. remark: in standard definition mode, only 8 of the 10 available signal lines of the d1 interface are used. the two lsb lines are fixed to zero. see ta bl e 11 to ta bl e 16 for code description fig 12. anc vbi data insertion in d1 table 11: vbi header/data codes name function sav start of active video did data identifier: ignored, has to be set to 0x11h sdid sliced data identification: ignored, has to be set to 0x11h bc byte count describes the number of succeeding decoded data bytes idi1 internal data identification 1: op, fid, linenumber[8:3] idi2 internal data identification 2: op, linenumber[2:0], data type d1-ddc data bytes eav end of active video table 12: vbi data header format ln = line number, bc = byte count, dt = data type code d9 d8 d7 d6 d5 d4 d3 d2 sdid 1 1 1 1 1 1 1 1 did 1 1 1 1 1 1 1 1 bc - - bc5 bc4 bc3 bc2 bc1 bc0 idi1 - field id 0=field 1 1=field 2 ln8 ln7 ln6 ln5 ln4 ln3 idi2 - ln2 ln1 ln0 dt3 dt2 dt1 dt0 table 13: sav/eav codes ntsc line number f v h (eav) h (sav) 1-3 1 1 1 0 4-19 0 1 1 0 20-263 0 0 1 0 ff 00 00 eav ff ff 00 did sdid bc idi1 idi2 d1 d2 ddc1 ddc ff 00 mdb646 00 sav timing reference code end active video timing reference code start active video anc header internal header horizontal line blanking interval sliced data
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 16 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] p0 to p3 are protection bits and calculated in the following way: p3=v^h, p2=f^h, p1=f^v, p0=f^v^h 264-265 0 1 1 0 266-282 1 1 1 0 283-525 1 0 1 0 table 14: sav/eav codes pal line number f v h (eav) h (sav) 1-22 0 1 1 0 23-310 0 0 1 0 311-312 0 1 1 0 313-335 1 1 1 0 336-623 1 0 1 0 624-625 1 1 1 0 table 15: sav/eav sequence sav/eav d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 preamble 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 status word 1 f v h p3 p2 p1 p0 0 0 table 16: supported data types data type standard 0000 teletext eurowst 0010 vps video programming service 0011 wss wide screen signalling 0100 closed caption 1100 us nabts 1111 programming (subaddr1-data1-subaddr2-data2...) table 13: sav/eav codes ntsc ?continued line number f v h (eav) h (sav)
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 17 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.1.6 primary video channel figure 13 illustrates the different modes of o peration for the prim ary video channel. pnx8510/11 supports color space conversi on only in the primary rgb standard definition data path. the fixed coefficients of this color space matrix are as follows: r = y + 1.371 x cr g = y - (0.336 x cb + 0.698 x cr) b = y + 1.732 x cb 7.1.7 secondary video channel the secondary display consists of the y an d uv processing data path of a video encoder only. the synchronization informati on will be extracted from the incoming d1 data stream. the structure of the secondary display pipe is shown in figure 14 . standard definition operating mode fig 13. primary display pipe mdb647 10 10 10 24 16 8 10/8 input interface mixer y-processing cvbs/y-dac r/c-dac g/c r /y-dac b/c b -dac sync extract uv-processing sync clk-divider macrovision (1) blanking macrovision (1) insertion delay comp color space matrix rgb- mode d1 clk input system clk video encoder rgb-pipe standard definition operating mode fig 14. secondary display pipe mdb648 10/8 10 10 input interface mixer y-processing cvbs/y-dac c-dac uv-processing sync macrovision (1) d1 video encoder
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 18 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.1.8 pal/ntsc/secam encoder the pal/ntsc/secam encoder accepts the yu v data and encodes it into an ntsc, pal or secam video signal. from y, u and v data, the encoder generates luminance, chrominanc e and subcarrier outp ut signals, suitable for use as cvbs or separate y and c signals. luminance is modified in gain and in offset (offset is programmable to enable different black level setups). in order to enable easy analog post filtering, luminance is interpolated from a 13.5 mhz data rate to a 27 mhz data rate, providing luminance in 10-bit resolution. this f ilter is also used to define smoothed transients for synchronization pulses and the blanking period. chrominance is modified in gain (programmable separately for u and v). the standard dependent burst is inserted before baseband color signals are interpolated from a 6.75 mhz data rate to a 27 mhz data rate. one of the interpolation stages can be bypassed providing a higher color bandwidth, which can be used for y and c output. the register bits fsc0 to fsc3 set the subcarrier frequency. to make sure the subcarrier is locked to the line frequency, as the standards require, the sync generator is able to reset the subcarrier generation periodically. this feature is controlled by the phres (register multictl, offset 0x6e) programming bits. these features are available to generate a standard interlaced signal; they will not work in non-interlaced mode. a crystal-stable master clock of 27 mhz, which is twice the ccir line-locked pixel clock of 13.5 mhz, is received from the interfac e clock pins. the encoder synthesizes all necessary internal signals, color subcarrier frequency, and synchronization signals from that clock. for ease of analog post filtering, the sig nals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. hd operation mode fig 15. primary display pipe mdb649 demux bypass y/r-dac u/c b /p b /g-dac v/c r /b-dac gain control sync-raster generator up-sample bypass d1-interface sync extract (1) d1-interface sync extract sync-insert level-shift sync-shaper cblank secondary d1 primary d1 v/o_e v/o_e h h v
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 19 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. programming flexibility includes ntsc-m, pa l-b, secam main standards as well as other variations. a number of possibilitie s are provided for setti ng different video parameters, such as: ? black and blanking level control ? color subcarrier frequency ? variable burst amplitude the sync generator generates all the signals required to control the signal processing, provide the composite sync signal, insert the color burst, etc. the encoder includes a cross-color reduction filter to reduce cross talk between the luminance and chromi nance channels. in the cvbs signal, the signal amplitude is reduced by 15/16 to avoid overflow. 7.1.9 luminance and chrominance processing the y processing provides a high performance 5 mhz lowpass filter. it adjusts the level range according to the standard and inserts the sync and blanking pulses. the insertion stage generates the correct pulse shapes. no further processing is necessary of the d/a converters for this purpose. chroma processing operates on the baseband signals as long as possible. at first, the signal amplitudes are adjusted and the burst is inserted. afterwards the signals are passed through a 1.4 mhz lowpass filter. this filter can be switched to a higher cut-off frequency to allow more chroma bandwidth with s-video. the quadrature modulator uses a dto (discr ete time oscillato r) with 32-bit resolution for the subcarrier generation. even with this high resolution, the dto cannot generate the carrier locked to the line frequency as the standards require without further means. so the sync generator is able to reset the dto periodically. this feature is controlled by the phres programming bits. these modes may only be switched on if the encoder is programmed to generate a st andard signal; they will not work in non-interlaced mode.
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 20 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 16. luminance transfer characteristic 1 handbook, full pagewidth 6 (1) (2) (4) (3) 8101214 6 0 024 mgd672 ? 6 ? 12 ? 18 ? 30 ? 24 ? 36 ? 42 ? 54 ? 48 f (mhz) g v (db) fig 17. luminance transfer characteristic 2 table 17: luminance transfer characteristics register ccrs, offset 0x5f defines th e luminance transfer characteristics ccrs luminance transfer characteristics 01 (1) 10 (2) 11 (3) 00 (4) handbook, halfpage 02 (1) 6 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 mbe736 4 f (mhz) g v (db)
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 21 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 18. chrominance transfer characteristic 1 handbook, full pagewidth 6 8 10 12 14 6 0 024 mbe737 ? 6 ? 12 ? 18 ? 30 ? 24 ? 36 ? 42 ? 54 ? 48 f (mhz) g v (db) (1) (2) fig 19. chrominance transfer characteristic 2 table 18: chrominance transfer characteristics register scbw, offset 0x61 defines t he chrominance transfer characteristics scbw chrominance transfer characteristics 1 (1) 0 (2) handbook, halfpage 0 0.4 0.8 1.6 2 0 ? 4 ? 6 ? 2 mbe735 1.2 f (mhz) g v (db) (1) (2)
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 22 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.1.10 sync generator the sync generator is the timing master of the encoder. it generates all the signals required to control the signal processing, provide the composite sync signal, insert the color burst, etc. via the fise control bit (register stdctl, offset 0x61), the circuit can be set to generate 50 hz patterns for e.g., pal b or 60 hz patterns (ntsc m). it is possible to modify the number of lines per field by 0.5 lines to generate a non-interlaced output signal. the sync genera tor also provides hs (horizontal sync), vs (vertical sync) and o_e (odd/even) signals to control the rest of the encoder. fig 20. luminance transfer characteristic in rgb handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb708 ? 6 ? 12 ? 18 ? 30 ? 24 ? 36 ? 42 ? 54 ? 48 f (mhz) g v (db) fig 21. color difference transfer characteristic in rgb handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb706 ? 6 ? 12 ? 18 ? 30 ? 24 ? 36 ? 42 ? 54 ? 48 f (mhz) g v (db)
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 23 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.1.11 macrovision? - pnx8510 the encoder supports macrovision ? anti-taping for both ntsc and pal. there is no macrovision? insertion for secam defined, however for agc pseudo sync and bp pulses the same settings used for pal coul d be used for secam. the different steps of this process can be programmed separately. the macrovision? control block provides all necessary timing and level info rmation for inserting the correct pulses in the cvbs/y/c/rgb/yuv data stream. furthe rmore it provides the signals used to modify the subcarrier generator according to the macrovision? burst inversion requirements. the encoder uses a blanking level during the vertical blanking interval that is defined by the value of blnvb, thus providing two different programmable blanking levels. outside vertical blanking, value of blnnl is effective, which should be reduced according to macrovision? requirements. the copy protection means can be activated independently by the respective control bits. the macrovision? registers and definition of each of these register s are defined in a separate macrovision? supplement document. remark: macrovision? is not available in pnx8511. 7.2 hd data path the high definition data path of the pnx8 510/11 ic features an up-sampling filter, gain control and a universal sync insertion engine. input formats supported by the high definition data path are: ? double d1 mode:16/20 bit 422 (8/ 10 bit for y and 8/10 bit for u/v); demux_mode of register vmuxctl, offset 0x95 is set to 3?b011 ? single interface hd 422 m ode (uyvy 422 d1 fo rmat); demux_mode of register vmuxctl, offset 0x95 is set to 3?b100 ? single interface 444 (rgb/yuv 444 format); demux_mode of register vmuxctl, offset 0x95 is set to 3?b001 ? full 24/30 bit parallel input mode (yuv/rgb 444 formats); vmode of register miscctrl, offset 0xa5 is set to zero rgb and yuv data types are accepted. howe ver, there is no color space conversion in the hd data path so the input data ty pe has to match the display data type. the up-sampling filter can be applied to convert incoming 422 data formats to 444. the data path also provides individual gain control for rgb/yuv which allows a +/-0.5x amplitude change (hd_gain_ry, hd_gain_gu, hd_gain_bv control registers). the hd sync insertion module following the f ilter and gain control circuits provides flexible insertion of synchronization signal s into the y, y and v or r, g and b data paths. the insertion can be chosen on a component basis (y/r_sync_ins_en, u/g_sync_ins_en, v/b_sync_ins_en contro l registers) and the sync generator provides individual tables for the components. a more detailed description of the sync generator can be found in the next paragraph.
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 24 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.2.1 hd-sync generator module this section describes the operation and programming of the high definition (hd) video data path sync unit. the module?s purpose is to provide the vi deo data path that bypasses the digital video encoders with the appropriate synchronization pattern. the module design provides maximum flexibility in terms of raster generation for all interlaced and non-interlaced atsc formats. the sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values at specified times in the outgoing data stream. it can also be used to generate digital signals associated with time events. they can be used as digi tal horizontal and vertical synchronization signals. the sync raster generation is fully programmable to accommodate different requirements. the raster generation can be either progressive or interlaced. digital sync signal generation (horizontal, vertic al and blank) as well as analog embedded sync generation are supported. the picture position is adjustable through the programmable relation between the sync pulses and the video contents. the generation of embedded analog sync pulses is bound to a number of events which can be defined for a line. several of these line-timing definitions can exist in parallel. for the final sync raster composition a certain sequence of lines with different sync event properties has to be defined. the sequence specifies a series of line types and the number of occurr ences of this specific line type. after the sequence has completed, it restarts from the beginning. in this way, the sync raster generation is generic and can be ad opted to different standards (different sync shapes, various h-timing, interlaced, progre ssive...). however, to generate a stable picture, it is important that the sequence fits precisely to the incoming data stream in terms of the total number of pixels per frame. the sync engine?s flexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. the list dependencies are illustrated in figure 22 .
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 25 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. the first table is called ?line_count_array? and serves as an array to hold the correct sequence of lines composing the synchroniz ation raster. it can contain up to 16 entries. each entry holds a 4-bit index (counted from 1 through 16)) and a 10-bit counter value. the 4-bit index is a pointer to a line in the next table called ?line_type_array.? a 10-bit counter value specifies how often this partic ular line is repeated. if the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries. this table has to be terminated with a dummy entry containing a ?0? index and ?0? line count. the second table, ?line_type_array? holds up to 15 entries (counted from 1 through 15). each entry can contain up to eight index pointers which point to another table called, ?line_pattern_array.? these pointers represent parts of a line raster. a line may be split up into a sync, a blank and an active portion followed by another blank portion, which would require four index pointers in one entry of the table. it is possible to have less than eight index pointers in any entry, in which case those index pointers should be filled with ?0. the third table is called ?line_pattern_arra y? and it can contain a maximum of seven entries (counted from 1 though 7). the entries are used to define portions of a line representing a certain value for a certain numb er of clock cycles. each of these seven entries can store up to four groups of ?duration, select and value index.? it is possible to have less than four groups in any entry, in which case those gr oups should be filled fig 22. sync engine list dependencies mdb650 3 3 10-bit duration 1-bit select 3-bit value index 10-bit duration 1-bit select 3-bit value index 10-bit duration 1-bit select 3-bit value index 10-bit duration 1-bit select 3-bit value index 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4-bit line type index 10-bit line count 10-bit value r/y-vallue_array 8 entries 10-bit value g/u-vallue_array 8 entries 10-bit value b/v-vallue_array 8 entries line_count_array 16 entries line_type_array 15 entries line_pattern_array 7 entries line_count_ptr event_type_ptr pattern_ptr line_type_ptr line_pattern_ptr
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 26 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. with 0. ?duration? is a 10-bit value representing the number of clock cycles. ?select? indicates whether the value is actually inserted into the video data stream or not. ?value index? is a 3-bit index into the next table in the linked list called ?value array.? certain bits of the ?value index? can also be used to generate a digital sync raster provided at the h- and v-sync outputs of the pnx8510/11. ?value array? can hold up to 8 values (c ounted from 0 though 7) which are 10-bit signed 2?s complement. 7.2.2 trigger generation to ease the trigger setup for the sync generation module, a set of registers is provided to set up the screen raster defined as width and height. a trigger position can be specified as an x, y coordinate within the overall dimensions of the screen raster. if the x, y counter matches the specified coordinates, a trigger pulse is generated which pre-loads the tables with th eir initial values. refer to the 1080i example for the trigger programming. important notes ? the ?duration? in the ?line_pattern_array? that needs to be programmed should be 1 cycle less than the actual duration required. ? for the registers lcnt_array_adr (offs et 0x82), ltype_ar ray_adr (offset 0x86), lpatt_array_adr (offset 0x8e), ?addr+1? should be written to finish writing the data meant for ?addr,? for example: for the registers lcnt_array_adr (offs et 0x82), ltype_ar ray_adr (offset 0x86), lpatt_array_adr (offset 0x8e), ?addr+1? should be written to finish writing the data meant for ?addr,? for example: ltype_array_line1 = 0x14 ltype_array_line2 = 0x05 ltype_array_line3 = 0x00 ltype_array_line_adr = 0x01 note the next address, 0x02, is written to fi nish writing to the previous address 0x01. ltype_array_line_adr = 0x02 ltype_array_line1 = 0x14 ltype_array_line2 = 0x03 ltype_array_line3 = 0x00 ltype_array_line_adr = 0x02 note the write to next address, 0x03 ltype_array_line_adr = 0x03 ltype_array_line1 = 0x0c ltype_array_line2 = 0x03
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 27 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. ltype_array_line3 = 0x00 ltype_array_line_adr = 0x03 note the write to next address, 0x04 ltype_array_line_adr = 0x04 ? the hd sync generator inserts a definable sync pattern (that normally includes blanking) into the video line. this includes a ?select? bit [in the line_pattern_array] which determines whether the current portion of the line should display video or generated sync. each portion of the line has a color valu e defined, which will be displayed if select=1. there is a 1 pixel path difference between ?select? and ?value?, resulting in the momentary display of the color value for 1 pixel width until the select bit switches active video to the output display. the work around for the above problem is to ensure that the value array entry for the ?active? portion of the line is set the same as the previous portion of the line. this will normally mean setting the value to blanking level. this will ensure that during the 1 clock path difference, the color value outp ut will be the same as for the previous portion of the line. this will remove the observed spike. the listing below outlines an example on how to set up the sync tables for a 1080i hd raster: // hd-sync config file for 1080i #line_count_array //index //line_count ------------------ 25//5 lines vsync 41//1 line sync -black-sync-black 614//14 lines blank 1537//537 lines active video 65//5 lines blank 51//1 line sync -black-sync-blank 24//4 lines sync 31//1 line sync blank sync black 615//15 lines blank 1537//537 lines active video 65//5 lines blank 00//dummy lines 00//dummy lines 00//dummy lines 00//dummy lines 00//dummy lines #line_type_array //p8p7p6p5p4p3p2p1 --------------- 00000034 //sync-full active line 00002424 //sync-half blank-sync-half blank 00001424 //sync-half bla nk-sync-half black 00001414 //sync-half black-sync-half black 00002414 //sync-half black-sync-half blank 00000054 //sync-full line black 00000000 00000000
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 28 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 00000000 00000000 00000000 00000000 00000000 00000000 00000000 #line_pattern_array //d=duration s=se lect v=value //d4s4v4d3s3v3d2s2v2d1s1v1 ------------------- 000000431387913 //half line black 000000431387910 //half line blank 431395906959065913 //full active line 000871343124311 //sync pulse 431395913959135913 //full line black 000000000000 000000000000 #value_array //signed values // yuv -------------- -51200//broad pulse level -512-432-432//lower sync tip 102432432//upper sync tip -20400//black/blank level org 000 000 000 000 #other //trigger_line // preload of the line count in //addr 0x9a-0x99 -hex values 99 3 9a 00 //trigger_duration // preload of duration of the line pattern array //addr 0x9c-0x9b -hex values 9c 0 9b 2 //trigger pointer 9d 0x11
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 29 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. // bit 1:0 loads the counter value of line count array // bit 7:4 loads the counter value of the line pattern array //sync raster //sync height ae 0x64 af 0x04 //sync width b0 0x97 b1 0x08 //sync trigger pos //trigger pos x b4 0x15 b5 0x00 //trigger pos y b2 0x15 b3 0x00 a complete example of register settings for 1080i is given in section 9 . the listing below outlines an example on how to set up the sync tables for a 720p raster: // hd-syn config file for 720p #line_count_array //index line_count ----------------------------------- 25//5 lines vsync 320//20 lines blank 1360//360 lines active video 1360//360 lines active video 35//5 lines blank 00//dummy lines 00//dummy lines 00//dummy lines 00//dummy lines 00 #line_type_array
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 30 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. //p8p7p6p5p4p3p2p1 ------------------------------------- 00000034 //sync-full line active 00000024 //sync-full line blank (vsync) 00000054 //sync-full line black (v-blanking) 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 #line_pattern_array //dur4sel4val4dur3sel3val 3dur2sel2val2dur1sel1val 1 ------------------------------------------------------- 000000000000 //empty 00069137141071410 //full line blank 6913639006390014913 //full line active 000691339123911 //sync pulse 6913639136391314913 //full line black 000000000000 000000000000 #value_array y //signed values yuv ------------------------ -51200//broad pulse level -512-432-432//lower sync tip 102432432//black/blank level org 000 000 000 000 7.2.3 signature analysis pnx8510/11 allows the signature analysis to be done on both primary and the secondary video channels and read the tw o signatures separately. the signature analysis is done on the upper 8 bits of th e interface. the video channel select for the signature analysis is defined by the ?s ig_select? of the si gctrl (offset 0xba) register. the signature is calculated as per the following crc algorithm: // * this is a simple table bas ed crc-16 that computes the crc // * four bits at a time. this requires a small (16 entry) lookup table. // * lookup table for non-reversed parallel crc algorithms // unsigned int crc16_table[16]={ // 0x0000, 0x8005, 0x800f, 0x000a,
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 31 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. // 0x801b, 0x001e, 0x0014, 0x8011, // 0x8033, 0x0036, 0x003c, 0x8039, // 0x0028, 0x802d, 0x8027, 0x0022 // }; // // * unlike the serial method, this algorithm does not require any additional // * operations to finish the crc after the message is processed // * this routine uses crc1 to hold the crc. // */ // // void parallel_crc1(c) // int c; // { // int r1 ; // // /* calculate crc using the 4 bit lut method */ // /* upper 4 bits */ // r1 = crc16_table[((crc1>>12) & 0xf) ^ ((c & 0xf0) >> 4)]; // crc1 = ((crc1 << 4) & 0xfff0) ^ r1; // // /* lower 4 bits */ // r1 = crc16_table[((crc1>>12) & 0xf) ^ (c & 0x0f)]; // crc1 = ((crc1 << 4) & 0xfff0) ^ r1; // } 7.2.4 limitations of the video pipe in all hd modes, the video encoder will be s witched off. either a separate sync signal or the embedded syncs of the d1 input ca n be used to generate the sync raster driving the display device. 7.3 audio pipeline the pnx8510/11 has two independent stereo channels, each connected to a separate audio interface. the primary audi o channel is usually associated with the primary video channel and carries the accompanying sound information. the
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 32 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. secondary audio channel usually carries the audio belonging to the record (secondary) video channel. because they might originate from different sources, the two interfaces are operated by independent clocks. mute on/off is programmable by a register setting. ta b l e 19 describes the expected audio performance. the audio path has three general blocks: input, interpolation, and dac. ? the input is, by default, a 24-bit i 2 s interface. however, it can be programmed to accept other formats. ? the interpolator scales, filters and oversamples the incoming data by 64 x its sampling frequency. the result goes to a no ise shaper, which shifts in-band noise to frequencies well above the audio spectrum. this provides a very high signal-to-noise ratio. ? finite impulse response dacs convert the 1-bit data stream to analog output voltage. 7.3.1 audio interface operation the audio interfaces can be operated in either slave or master mode: ? in slave mode, all required clocks (system clk, sck and ws) must be generated externally and must be synchronous with each other. ? in master mode, the pnx8510/11 only gets the system clk and generates sck and ws clocks synchronously to the applie d system clk. in this mode, system clk is equal to 128 x fs where fs is the audio sampling frequency. table 19: audio performance parameter qfp100 dynamic range 85db s/(n+disto.) >85db fig 23. audio path block diagram mdb651 fir-dac-l ? noise shaper ? noise shaper interpolator left/right interpolator left/right fir-dac-r fir-dac-l fir-dac-r primary i 2 s-bus secondary i 2 s-bus
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 33 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. audio input timing figure 24 and figure 25 illustrate the different mo des of operation for the i 2 s interface used in the pnx8510/11. 7.3.2 mute modes the audio modules of the pnx8510/11 have several mute functions. the mute operation is controlled via the bits ?quickmute, and mutemode? of the programming register, interpolator _reg2(offset 0x00fd). justification bit is not delayed. fig 24. input formats mdb652 msb lsb msb lsb msb lsb msb lsb : position may vary with wordsize : position fixed msb first / msb justified format (msb) msb first / lsb justified format (japanese 1 2 s-bus, 16, 18, 20, 24 bit) sck sd ws ws justification bit is one bit clock delayed. fig 25. input format mdb653 msb lsb msb lsb : position may vary with wordsize : position fixed msb first / msb justified format (philips i 2 s-bus) sck sd ws table 20: i 2 s signals port description sck bit clock sd pcm data ws word select; left and right clock is equal to the sample rate.
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 34 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. quick mute this is an overriding quickmute on the master channel, which mutes the interpolator output signal in 32 samples using the co sine roll-off coefficients instead of 32x32 samples to mute the output. this means whenever the quickmute register is set to one, independent of what the mute setting of the micro controller is, the output is muted. mute mode this register sets the mute mode for the master mute to either soft mute (setting is ?0?) or to quick mute (setting = ?1?). for the master channel the quickmute function and the micro controller mute function are or?d. figure 26 shows the signal flow for the mute control. 7.4 programming interface the configuration of the various interface modes and the digital video encoder setup can be controlled via an i 2 c interface or a special vbi data packet sent during the horizontal blanking interval. with the vbi programming interface, a reliable real-time programming for the pnx8510/11 video bloc ks can be accomplished. for instance, this mode makes it very easy to carry the necessary programming data over to the digital encoder to encode a certain telete xt packet in a specific scanline without table 21: mute mode control quick mute micro controller mute function 0 0 no mute 0 1 1 micro controller mute...mute mode depends on the ?mutemode? setting. 1 x overriding quick mute function table 22: mute mode function while in mute mode, releasing the ?mute? bit applies a graduated cosine startup mute mode function 0 mute function via micro controller interface is set to ?soft mute.? 1 mute function via micro controller interface is set to ?quick-mute.? fig 26. mixing possibilities in interpolator 4v0 mdb654 de-emphasis volume bass boost treble hb (1) volume mute mute vm1 channel 1 master channel mutemix double speed input conditional shift when mixing mute2 mute1 mute1 0.25 db steps 0.25 db steps de-emphasis volume mute vm2 channel 2 + +
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 35 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. extensive buffering. the format for programming registers in the pnx8510/11 via the vbi interface can be found in section 7.1.5 . note that reprogramming clocks and audio registers are not poss ible via the vbi interface. the pnx8510/11 is an i 2 c slave device only. it uses four dedicated slave addresses to address the primary, secondary, audio and remaining control registers. the i 2 c address set can be configured during reset with a pull-up or pull-down combination of gpio pins. ta bl e 23 shows the register sets and the relation ship with the ?xy? bits in the address structure. ta bl e 24 shows an example of how the i 2 c device addresses are determined. a detailed description of all programming registers can be found in section 8 . 7.5 gpio block gpios are multi-purpose pins. they may be programmed as input/output and used to carry signals into the ic or to monitor the status of the ic. the selection of these i/o pins is controlled through programmable registers. the gpio module can be programmed via subaddress 90-95 of the primary video pipe. the gpio pins operate in two basic modes; bootstrap mode and gpio mode. during chip reset the gpios are in bootstrap mode. the status of all gpio pins is monitored and used to determine the set of i 2 c device addresses the ic responds to. after the chip reset is released, the gpio pins may be used in gpio mode. in output mode each gpio pin can be set to logic one or zero by programming the appropriate register. in input mode the status of each gpio can be monitored by reading the table 23: relation of ?xy? with register sets address= gpio5-gpio4-xy-gpio3-gpio2-gpio1-r/w register set x y video 1 0 0 video 2 0 1 audio 1 / video 1 and audio 1 clocks 1 0 audio 2/ video 2 and audio 2 clocks 1 1 table 24: i 2 c address determination register set selection example video 1 iic address selection example: gpio5-2 are set to logic one and gpio1 is set to zero during the pnx8510/11rest. address = gpio5-gpio4-xy -gpio3-gpio2-gpio1-r/w address = 1-1-xy-1-1-0-r/w video1 = 1-1-0-0-1-1-0-r/ w = 0xcc(write), 0xcd(read) video2 = 1-1-0-1-1-1-0-r/w = 0xdc (write), 0xdd(read) audio1 = 1-1-1-0-1-1-0-r/w = 0xec(write), 0xed(read) audio2 = 1-1-1-1-1-1-0-r/w = 0xfc(write), 0xfd(read) video 2 audio 1 / video 1 and audio 1 clocks audio 2/ video 2 and audio 2 clocks
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 36 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. appropriate status register. in addition to the register-driven i/o mode, some of the gpio pins are used to reflect the status of internal signals. some gpio pins are also used as additional inputs to functional units if operated in input mode. 7.5.1 operation gpio set during reset during reset the gpio output is disabled. gpio_in is stored as gpio_in_stored and retains its value until the next reset. this stored value determines the i 2 c device addresses. after reset, gpio pins can be programmed for output with the oen and out_sel bits. checking/setting the gpio status each gpio pin is multiplexed fo ur times to increase usability. figure 27 outlines the internal structure of one gpio pin. in outp ut mode the selection of the signal routed out to a gpio pin is performed with the out_sel register bits. the oen bit is low active and enables the gpio output mode. if out_sel is set to 2?b11 and the oen bit is set to zero, the gpio pin can be set or reset by writing a one or zero into the status location of the gpio register. a ll other out_sel settings are listed in ta bl e 29 . to read the external status of a gpio pin, the oen needs to be set to one to avoid conflicts with signals routed out of the chip. if gpio_in_en4 is set to one, the status of the gpio pin can be monitored by reading the status bit of the appropriate gpio register. the function of all releva nt gpio_in/out signals are listed in figure 27 and ta bl e 25 . fig 27. operation modes for one gpio in the pnx8510/11 table 25: specific gpio assignments signal description gpio5_out1 composite sync secondary encoder gpio5_out2 vertical sync primary encoder gpio5_in3 30-bit parallel video input mode: bit[1] = red channel mdb655 gpio_in_en1 gpio_in4 gpio_in_stored gpio_in3 gpio_in2 gpio_in1 gpio_out1 gpio_out2 gpio_out3 gpio_out4 gpio_in_en2 gpio_in_en3 gpio_in_en4 gpio_in gpio_out out_sel gpio oen
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 37 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.6 clock module all of the pnx8510/11 modules receive their input clocks from the clocks module. the top level structure of the clocks module is figure 28 . the pnx8510/11 in normal operation mode re ceives four external clocks. two clocks dv_clk1 and dv_clk2 are the clocks used for the primary and secondary video data paths. the other two clocks assemble the audio over-sampling clocks for the primary and secondary audio channel. gpio4_out1 data request secondary encoder gpio4_out2 composite sync primary encoder gpio4_in3 30-bit parallel video input mode: bit[0] = red channel gpio3_out1 enable y secondary encoder (1/2 of the encoder operation frequency) gpio3_out2 odd/even signal primary encoder gpio3_in1 real time control input primary encoder gpio3_in2 real time control input secondary encoder gpio3_in3 30-bit parallel video input mode: bit[1] = green channel gpio2_out1 odd/even signal secondary encoder gpio2_out2 data request primary encoder gpio2_in3 30-bit parallel video input mode: bit[0] = green channel gpio1_out1 vertical sync secondary encoder gpio_in3 30-bit parallel video input mode: bit[0] = blue channel all other settings are reserved for future use table 25: specific gpio assignments ?continued signal description fig 28. clocks module mdb656 i 2 c-bus decoder module clocks_video_sub_1 clocks_video_sub_2 clocks_audio_sub_1 clocks_audio_sub_2 clk_dv1_if dv_clk1 dv_clk2 i2s_aos1_clk i2s_aos2_clk clk_dv1_proc clk_dv2_if clk_dv2_proc sclk_a1 ws_a1 sclk_a2 ws_a2
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 38 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. the pnx8510/11 video clocks are used to create two internal clocks: one for operating the video input interface (clk_dv1_ if, clk_dv2_if), and one for operating the main video processing pipeline (clk_dv1_proc, clk_dv2_proc). the audio interface normally operates in slave mode (over-sampling clock, word select and bit clock are provided from the externally connected i 2 s master). however the pnx8510/11 can be operated in master mode. this mode only requires the over-sampling clock to be provided. the bit clock and the word select signals are subdivided from the over-sampling clock and provided to the chip pins. remark: both video clocks (dv_clk1 and dv_clk2) and an audio clock (i2s_aos1_clk) have to be connected to t he device for proper functioning of the i 2 c programming interface. these clocks must be provided before the reset line (reset_n) is pulled high to ensure correct initialization of th e device. for more information refer to section 10.4 . if the two video pipelines are sourced by only one video input interface operating in sliced mode, both video pipelines must rece ive the same input clock originating from the same sliced data source. 7.6.1 clocks video submodule the generation of the various clock signals needed for video pipelines takes place in the clocks video module. figure 29 shows a block diagram of this module. the configuration registers for the clocks module can be found in section 8.2 . 7.6.2 clocks audio submodule the input clocks for the audio block are generated in the clocks audio submodule. figure 30 shows a block diagram for this submodule fig 29. clocks video submodule mdb657 clock divider & de-gilitcher clocks_sel clock divider & de-gilitcher clk_dv_if_out dv_clk sel_v test test div by 1, 2, 3 or 4 clocks_sel div by 1, 2, 3 or 4 dv_clk dv_clk clk_dv_proc_out
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 39 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.7 test mode this section describes how the analog test modes are implemented in the pnx8510/11. note that these test modes ar e intended for production test only. the chip needs to be brought into analog test mode via the jtag boundary scan controller. once the chip is in analog te st mode the different test modes can be enabled via the gpio pins. the data input for the video dacs is provided via the dv1 interface for dacs 1 through 4 and via the dv2 interface for dacs 5 and 6 respectively. the ?main switch? for the test mode is controlled by the jtag boundary scan controller. once the chip is in analog test mode, the gpio pins can be used to select certain combinations outlined in the tables. for the video dacs 1 to 4, the primary 10-b it d1 interface (dv1_in[9:0]) provides the 10-bit input. video dacs 5 and 6 are stimulated through the secondary d1 interface (dv2_in[9:0]) the serial audio data streams for the first stereo pair are provided through the i2s_in1_sd and the i2s_in1_ws pins. the audio dac pair 3 and 4 get their serial data through pins i2s_in2_sd and i2s_in2_ws. fig 30. clocks audio submodule mdb658 4-bit divider 9-bit divider sclk_a clk_a sel_a sck_in ws_in test_a i2s_aos_clk ws_a table 26: video dac test modes gpio2 gpio3 test 0 0 vdac1 and vdac5 active 0 1 vdac2 and vdac6 active 1 0 vdac3 and vdac5 active 1 1 vdac4 and vdac6 active table 27: audio dac test modes gpio4 gpio5 test 0 0 adac1/2 and adac3/4 stereo pair first and second channel off 0 1 adac1/2 stereo pair first channel active 1 0 adac3/4 stereo pair second channel active 1 1 adac1/2 and adac3/4 stereo pair first and second channel active
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 40 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. register descriptions the pnx8510/11 register space is divided into four different spaces. each of them is addressed by a different i 2 c device address. the first address space is dedicated to the primary video channel, the second space belongs to the secondary video channel. the third i 2 c address space accommodates th e registers that control the first audio channel. the fourth i 2 c space is used to address the secondary audio channel. the video channel registers are only listed once. because the secondary video channel does not support high definition or rgb output, its registers have some minor differences, which are noted in ta b l e 28 and ta bl e 29 as ?not present in secondary video channel.? the slave addresses are selectable during boot. the registers for the primary and secondary audio and video modules are identical, except as noted in the register definitions. ta bl e 28 and ta bl e 29 provide the offset?the base address is dependent on the module. the actual address spaces are determined at boot time according to the gpio settings. for more information refer to section 7.4 . fig 31. audio and video dac test modes mdb659 vdac1 vdac2 vdac3 vdac4 vdac5 vdac6 adac1 adac2 test decoder audio test decoder video i2s_in1_ws i2s_in1_sd gpio2 dv1_in[9:0] dv2_in[9:0] gpio3 gpio4 gpio5 adac3 adac4 i2s_in2_ws i2s_in2_sd 10 10 table 28: pnx8510/11 register summary descriptions with * have different meaning, or ar e not present in secondary video address space. see ta bl e 29 for more details. address name description video address space 0x00 status status register 0x1a msmt monitor sense mode threshold
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 41 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x1b msms monitor sense mode status 0x26 wss1 wide screen signaling data 0x27 wss2 wide screen signaling enable 0x28 bctl burst control 0x29 bctl2 burst control 0x2a cgd1 copy guard 0x2b cgd2 copy guard 0x2c cgd copy guard enable 0x2d dacctl dac control * 0x38 gain_y gain adjust for y compone nt (sd rgb/yuv data path) * 0x39 gain_uv gain adjust for uv compon ent (sd rgb/yuv data path) * 0x3a inpctl input control register * 0x54 vps1 video programming system 0x55 vps2 video programming system 0x56 vps3 video programming system 0x57 vps4 video programming system 0x58 vps5 video programming system 0x59 vps6 video programming system 0x5a chps color subcarrier phase 0x5b gainu gain adjust for u component 0x5c gainv gain adjust for v component 0x5d blckl black level adjust 0x5e blnnl blank level adjust 0x5f blnvb/ccr cross color reduction / blank level (during vertical blank) 0x61 stdctl video standard control 0x62 bsta burst amplitude control 0x63?66 fsc0-fsc3 color subcarrier frequency control 0x67 l21o0 closed captioning odd field 0x68 l21o1 closed captioning odd field 0x69 l21e0 closed captioning even field 0x6a l21e1 closed captioning even field 0x6c trgctl1 sd trigger control 0x6d trgctl2 sd trigger control 0x6e multictl sync and blank control 0x6f ttxctl vbi insertion control 0x70 adwhs active display window start 0x71 adwhe active display window end 0x72 adwhs/e active display window - msb 0x73 ttxhs ttx control table 28: pnx8510/11 register summary ?continued descriptions with * have different meaning, or ar e not present in secondary video address space. see table 29 for more details. address name description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 42 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x74 ttxhl/ttxhd ttx control 0x75 csynca composite sync control 0x76 ttxovs ttx insertion control odd field 0x77 ttxove ttx insertion control odd field 0x78 ttxevs ttx insertion control even field 0x79 ttxeve ttx insertion control even field 0x7a fal first active line 0x7b lal last active line 0x7c ttxctrl ttx format control 0x7e dttxl ttx mask 0x7f dttxl2 ttx mask 0x80 lcnt_array_line hd sync generator control * 0x81 lcnt_array_line hd sync generator control * 0x82 lcnt_array_adr hd sync generator control * 0x83?0x85 ltype_array_line hd sync generator control * 0x86 ltype_array_adr hd sync generator control * 0x87?0x8d l pat t _ a r r ay _ l i n e hd sync generator control * 0x8e l pat t _ a r r ay _ a d r hd sync generator control * 0x90?0x94 gpio5-gpio1 gpio control * 0x95 vmuxctl video input mode control * 0x96?0x97 value_array_line hd sync generator control * 0x98 value_array_adr/event _type_ptr hd sync generator control * 0x99?0x9a trigger_line hd sync generator control * 0x9b?0x9c trigger_duration hd sync generator control * 0x9d trigger_ptr hd sync generator control * 0x9e blank_y programmable blank level for y (sd rgb/yuv data path) * 0x9f blank_uv programmable blank level for uv (sd rgb/yuv data path) * 0xa0 rgb_ctrl color space matrix bypass enable * 0xa2 border_y border color 0xa3 border_u border color 0xa4 border_v border color 0xa5 miscctrl dac and trigger control * 0xa6 hdctrl hd video path control * 0xa7 sync_delay sync and vbi programming control 0xa8 blank_r/y blank offset control hd video path * 0xa9 blank_g/u blank offset control hd video path * 0xaa blank_b/v blank offset control hd video path * 0xae sync_height1 hd sync generator screen height * table 28: pnx8510/11 register summary ?continued descriptions with * have different meaning, or ar e not present in secondary video address space. see table 29 for more details. address name description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 43 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0xaf sync_height2 hd sync generator screen height * 0xb0 sync_width1 hd sync generator screen width * 0xb1 sync_width2 hd sync generator screen width * 0xb2 sync_trigpos_y1 hd sync generator vertical position control1 * 0xb3 sync_trigpos_y2 hd sync generator vertical position control2 * 0xb4 sync_trigpos_x1 hd sync generator horizontal position control1 * 0xb5 sync_trigpos_x2 hd sync generator horizontal position control2 * 0xb6 sig1 video signature * 0xb7 sig2 video signature * 0xb8 sig3 video signature * 0xb9 sig4 video signature * 0xba sigctrl video signature analyzer control * 0xbc blank_msbs blank offset control * 0xbe r/y value array line r/y value array data * 0xbf b/u value array line b/u value array data * 0xc0 g/v value array line g/v value array data * 0xc1 value array line msbs value array data msbs * 0xc2 dac1 adj coarse current control dac1 * 0xc3 dac2 adj coarse current control dac2 * 0xc4 dac3 adj coarse current control dac3 * 0xc5 dac4 adj coarse current control dac4 * 0xc6 dacc adj common current fine adjust for dacs 1-4 * 0xc7 hd_gain r/y gain adjust hd path * 0xc8 hd_gain g/u gain adjust hd path * 0xc9 hd_gain b/v gain adjust hd path * audio/clock address space 0x0000 clk_audio audio clock control 0x0001 clk_if video interface clock control 0x0002 clk_proc_div video processing clock control 0x0003 clk_dac_div video dac clock control 0x00f4 i 2 s_set_reg audio interface control 0x00f5?00fb feature_reg audio feature control 0x00fc interpolator_reg1 audio feature control 0x00fd interpolator_reg2 audio feature control 0x00fe audio dac power on register audio dac control table 28: pnx8510/11 register summary ?continued descriptions with * have different meaning, or ar e not present in secondary video address space. see table 29 for more details. address name description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 44 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.1 video address space table 29: pnx8510/11 video registers * indicates not present in secondary video channel bit symbol access value description offset 0x00 status 7 ver2 r 0 version id bit 2 6 ver1 r 0 version id bit 1 5 ver0 r 1 version id bit 0 4 ccrdo r - closed caption encoding done for odd field 3 ccrde r - closed caption encoding done for even field 2 unused - 1 fseq r - field sequence 1 = during first field of a sequence 0 = not the first field of a sequence 0 o_e r - status of the odd/even flag in the encoder registers 0x01 through 0x10 must be initialized to zero. offset 0x1a msmt 7:0 msmt r/w - monitor sense mode threshold for dacs comparator offset 0x1b msms 7 msm r/w 0 monitor sense mode 0 = off 1 = on 6:4 unused - 3 msms4* r - monitor sense status dac4 0 = comparator is inactive. 1 = comparator is active. 2 msms3* r - monitor sense status dac3 0 = comparator is inactive. 1 = comparator is active. 1 msms2 r - monitor sense status dac2 0 = comparator is inactive. 1 = comparator is active. 0 msms1 r - monitor sense status dac1 0 = comparator is inactive. 1 = comparator is active. registers 0x1c through 0x25 must be initialized to zero. offset 0x26 - wss1 7:0 wssd[7:0] r/w - wide screen signalling data bits 3:0 = aspect ratio encoding bits 7:4 = enhanced services offset 0x27 - wss2 7 wsson r/w 0 wide screen signalling enable 0 = wss switched off 1 = wss switched on 6 unused -
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 45 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5:0 wssd[13:8] r/w - wide screen signalling data bits 13:11 = reserved bits 10:8 = subtitles offset 0x28 - rtc1/bctl1 7 decfis r/w 0 field sequence detection via rtc 0 = field sequence as fise in address 61 1 = field sequence detection via rtc interface 6 deccol r/w 0 color detection via rtc interface 0 = color detection via rtc disabled 1 = color detection via rtc enabled note: the rtce bit must be set to 1 to enable this feature. 5:0 bs r/w 0x21 starting point of color burst in clk cycles from hsync pal=0x21 ntsc=0x25 offset 0x29 - bctl2 7:6 unused - 5:0 be r/w 0x1d color burst end point in clk cycles from hsync pal = 0x1d ntsc = 0x1d offset 0x2a - cgd1 7:0 cg r/w - copy guard information bits 7:0 note: the 14 lsbs of the byte carry the information encoded after the run-in. the 6 msbs have to carry the crcc bits in accordance with the definition of the cgms encoding format. offset 0x2b - cgd2 7:0 cg r/w - copy guard information bits 15:8 note: the 14 lsbs of the byte carry the information encoded after the run-in. the 6 msbs have to carry the crcc bits in accordance with the definition of the cgms encoding format. offset 0x2c - cgd 7 cgen r/w 0 copy guard enable 0 = disabled 1 = enabled 6:4 unused - 3:0 cg r/w - copy guard information bits 19:16 note: the 14 lsbs of the byte carry the information encoded after the run-in. the 6 msbs have to carry the crcc bits in accordance with the definition of the cgms encoding format. offset 0x2d - dacctl video data path 7 vbsen* r/w 1 dac3 control 0 = video dac 3 carries the green channel. 1 = video dac 3 carries the luminance channel. table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 46 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6 cvbsen r/w 1 dac1 control 0 = video dac 1carries the luminance channel. 1 = video dac 1 carries the cvbs channel. 5 cen* r/w 1 dac2 control 0 = video dac 2 carries the red channel. 1 = video dac 2 carries the chroma channel. 4:0 unused - registers 0x2e?0x37 must be initialized to zero. offset 0x38 - gain_y * 7:5 unused - 4:0 gain_y* r/w 0x1a gain adjust for y component in sd-rgb/yuv data path, two?s complement number to adjust the gain from -50% to +50% yout=yin x (1+ gain_y/32) offset 0x39 - gain_uv* 7:5 unused - 4:0 gain_uv* r/w 0x1a gain adjust for u/v components in sd-rgb/yuv data path, two?s complement number to adjust the gain from -50% to +50% uvout=uvin x (1+ gain_uv/32) offset 0x3a - inpctl 7 cbenb r/w 0 color bar generator 0 = color bar generation switched off 1 = color bar generation enabled (sd-cvbs/yc and sd-rgb/yuv modes only) 6 qualinvert* r/w 1 0 = leave the pixel qualifier untouched. 1 = invert the incoming pixel qualifier. 5 use_qual* r/w 0 use qualifier enable 0 = no qualifier is used, qualinvert should be set. 1 = the hsync input is used as slice qualifier in interleaved mode. 4 dedge r/w 0 double edge mode 0 = double edge mode off; either the interface is running at 2x speed to get interleaved data in or only non-interleaved data streams are accepted. 1 = input data is latched at positive and negative edge. the slice_dir register determines which data slice goes in which channel. 3 sd_hd* r/w 1 video mode switch 0 = hd data path in operation; encoder runs idle. 1 = sd data path in operation; encoder is in cvbs/yc or rgb mode. 2 u2c r/w 1 0 = y/r data channel coming from the d1 interface left unchanged 1 = y/r msb of data coming from the d1 interface is inverted. 1 m2c r/w 1 0 = u/g data channel coming from the d1 interface left unchanged 1 = u/g msb of data coming from the d1 interface is inverted. table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 47 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0 l2c* r/w 1 0 = v/b data channel coming from the d1 interface left unchanged 1 = v/b msb of data coming from the d1 interface is inverted. registers 0x3b through 0x53 must be initialized to zero. offset 0x54 - vps1 7 vpsen r/w 0 0 = video programming system data insertion disabled 1 = video programming system data insertion enabled 6:0 unused - offset 0x55 - vps2 7:0 vpsb5 r/w - fifth byte of video programming system data offset 0x56 - vps3 7:0 vpsb11 r/w - 11th byte of video programming system data offset 0x57 - vps4 7:0 vpsb12 r/w - 12th byte of video programming system data offset 0x58 - vps5 7:0 vpsb13 r/w - 13th byte of video programming system data offset 0x59 - vps6 7:0 vpsb14 r/w - 14th byte of video programming system data offset 0x5a - chps 7:0 chps r/w 0x0 phase of encoded color subcarrier (including burst) relative to horizontal sync. can be adjust ed in steps of 360/256 degrees. offset 0x5b, 0x5d(msb) - gainu 7:0 gainu r/w 0x7d variable gain for cb signal; input representation is in accordance with ccir656. this is the digital gain for sd-data path white to black = 92.5 ire gainu can be adjusted in a range from -2.17 x nominal to 2.16 x nominal gainu=0 (output subcarrier contribution of u = 0) gainu=0x76 (output subcarrier contribution of u = nominal) white to black = 100 ire gainu can be adjusted in a range from -2.05 x nominal to 2.04 x nominal gainu=0 (output subcarrier contribution of u = 0) gainu=0x7d (output subcarrier contribution of u = nominal) gainu=0x6a (nominal gain for secam encoding) offset 0x5c, 0x5e(msb) - gainv table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 48 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7:0 gainv r/w 0xaf variable gain for cr signal; input representation is in accordance with ccir656. white to black = 92.5 ire gainv can be adjusted in a range from -1.55 x nominal to 1.55 x nominal gainv=0 (output subcarrier contribution of v = 0) gainv=0xa5 (output subcarrier contribution of v = nominal) white to black = 100 ire gainv can be adjusted in a range from -1.46 x nominal to 1.46 x nominal gainv=0 (output subcarrier contribution of v = 0) gainv=0xaf (output subcarrier contribution of v = nominal) gainv=0x7f (nominal gain for secam encoding) offset 0x5d - blckl 7 gainu r/w 0 bit 8 of register 0x5b 6 decoe r/w 0 odd/even field control via rtc interface 0 = disabled 1 = enabled 5:0 blckl r/w 0x33 variable black level; input repr esentation is in accordance with ccir656. white to sync = 140 ire recommended blckl=0x3a blckl=0 (output black level = 29 ire) blckl=0x3f (output black level = 49 ire) output black level/ire=blckl x 2/6.29+28.9 white to sync = 143 ire recommended blckl=0x33 blckl=0 (output black level = 27 ire) blckl=0x3f (output black level = 47 ire) output black level/ire=blckl x 2/6.18+26.5 offset 0x5e - blnnl 7 gainv r/w 0 bit 8 of register 0x5c 6 decph r/w 0 subcarrier phase reset control via rtc interface 0 = disabled 1 = enabled 5:0 blnnl r/w 0x35 variable blanking level white to sync = 140 ire recommended blckl=0x2e blnnl=0 (output black level = 26 ire) blnnl=0x3f (output black level = 46 ire) output black level/ire=blckl x 2/6.29+25.4 white to sync = 143 ire recommended blckl=0x35 blnnl=0 (output black level = 26 ire) blnnl=0x3f (output black level = 46 ire) output black level/ire=blckl x 2/6.18+25.9 table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 49 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. offset 0x5f - blnvb/ccr 7:6 ccrs r/w 0x0 cross-color reduction filter settings for luminance path 00 = cross color reduction filter off 01 = filter is active; transfer characteristic 1 10 = filter is active; transfer characteristic 2 11 = filter is active; transfer characteristic 3 5:0 blnvb r/w 0x35 variable blanking level during vertical blanking interval is typically identical to the value of blnnl. offset 0x60 - must be initialized to zero offset 0x61 - stdctl 7:6 unused - 5 inpi r/w 0 0 = pal switch phase is nominal. 1 = pal switch phase is inverted compared to nominal if rtc is enabled. 4 ygs r/w 0 0 = luminance gain for white - black 100 ire for pal 1 = luminance gain for white - black 92.5 ire (for ntsc) including 7.5 ire set-up of black 3 secam r/w 0 secam enable 0 = secam encoding switched off 1 = secam encoding switched on (pal has to be 0) 2 scbw r/w 1 0 = enlarged bandwidth for chrominance encoding 1 = standard bandwidth for chrominance encoding 1 pa l r/w 1 0 = ntsc encoding (non alternating v component) 1 = pal encoding (alternating v component) 0 fise r/w 0 0 = 864 total pixel per line for pal 1 = 858 total pixel per line for ntsc offset 0x62 - rtcctl/bsta 7 rtce r/w 0 0 = no real time control of generated subcarrier frequency 1 = real time control of generated subcarrier frequency 6:0 bsta r/w 0x2f amplitude of color burst; input repr esentation is in accordance with ccir 601 white to black = 92.5 ire, burst = 40 ire, ntsc encoding bsta 0 to 2.02 x nominal recommended value bsta = 0x3f white to black = 92.5 ire, burst = 40 ire, pal encoding bsta 0 to 2.82 x nominal recommended value bsta = 0x2d white to black = 100 ire, burst = 40 ire, ntsc encoding bsta 0 to 1.90 x nominal recommended value bsta = 0x43 white to black = 92.5 ire, burst = 40 ire, pal encoding bsta 0 to 3.02 x nominal recommended value bsta = 0x2f fixed burst amplitude for secam encoding offset 0x63?0x66 - fsc0-fsc3 table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 50 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7:0 0x63=fsc0 0x64=fsc1 0x65=fsc2 0x66=fsc3 r/w 0x2a0 98acb ffsc: subcarrier frequency (in multiples of line frequency) fllc: clock frequency (in multiples of line frequency) fsc = round ((ffsc/fllc)x2^32) fsc3 most significant byte fsc0 least significant byte ntsc-m: ffsc 227.5, fllc 1716 -> fsc = 21f07c1f pal-b/g: ffsc 283.7516, fllc 1728 -> fsc = 2a098acb secam: ffsc 274.304, fllc 1728 -> fsc = 28a33bb2 offset 0x67 - l21o0 7:0 l21o0 r/w 0x0 first byte of closed captioning data, odd field offset 0x68 - l21o1 7:0 l21o1 r/w 0x0 second byte of closed captioning data, odd field offset 0x69 - l21e0 7:0 l21e0 r/w 0x0 first byte of closed captioning data, even field offset 0x6a - l21e1 7:0 l21e1 r/w 0x0 second byte of closed captioning data, even field offset 0x6b - must be initialized to zero. offset 0x6c - trgctl1* 7:0 htrig r/w 0x01 sets horizontal trigger phase related to encoder input. values above 1715 (fise=1) or 1727 (fise=0) are not allowed. increasing htrig decreases delay as of all internally generated timing signals. this register is for the sd path. reference mark: analog output horizontal sync (leading slope) coincides with active edge of rcv used for triggering at htrig=0x398. offset 0x6d - trgctl2* 7:5 htrig r/w 0x1 sets horizontal trigger phase related to encoder input.this register is for the sd path. 4:0 vtrig r/w 0x0 increasing vtrig decreases delays of all internally generated timing signals measured in half lines. variation range of vtrig = 0 to 0x1f offset 0x6e - multictl 7 unused - 6 blckon r/w 0 0 = encoder in normal operation mode 1 = output signal is forced to blanking level. this doesn?t shutdown the sync and leaves it running. 5:4 phres r/w 0x2 selects the phase reset mode of the color subcarrier. 00 = no phase reset or reset via rtc 01 = phase reset every two lines 10 = reset every eight fields 11 = reset every four fields table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 51 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3:2 ldel r/w 0x0 selects the luminance delay in reference to the chrominance 00 = no luma delay 01 = 1llc luma delay 10 = 2llc luma delay 11 = 3llc luma delay 1:0 flc r/w 0x0 this register is to control the sync. generator field length control 00 = interlaced 312.5 lines/field at 50hz, 262.5 lines/field at 60hz 01 = non interlaced 312 lines @50hz, 262 lines @60hz 10 = non interlaced 313 lines @50hz, 263 lines @60hz 11 = non interlaced 313 lines @50hz, 263 lines @60hz offset 0x6f - ttxctl 7:6 ccen r/w 0x00 closed caption enable 00 = line 21 encoding off 01 = enables encoding in field 1 (odd). 10 = enables encoding in field 2 (even). 11 = enables encoding in both fields. 5 ttxen r/w 0 0 = disables tele text insertion. 1 = enables teletext insertion. 4:0 sccln r/w 0x11 selects the actual line where closed caption or extended data are encoded. line = (sccln + 4) for m-systems line = (sccln +1) for other systems offset 0x70 - adwhs (horizontal) 7:0 adwhs7:0 r/w 0x5a active display window horizontal start bits 7 to 0 defines the start of the active tv display portion after the border color. values above 1715 (fise=1) or 1727 (fise=0) are not allowed. offset 0x71 - adwhe (horizontal) 7:0 adwhe7:0 r/w 0x5a active display window horizontal end bits 7 to 0 defines the start of the active tv display portion after the border color. values above 1715 (fise=1) or 1727 (fise=0) are not allowed. offset 0x72 - adwhs/e 7 unused - 6:4 adwhe10:8 r/w 0x6 active display window horizontal end bits 10 to 8. defines the start of the active tv display portion after the border color. values above 1715 (fise=1) or 1727 (fise=0) are not allowed. 3 unused - 2:0 adwhs10:8 r/w 0x1 active display window horizontal start bits 10 to 8 defines the start of the active tv display portion after the border color. values above 1715 (fise=1) or 1727 (fise=0) are not allowed. offset 0x73 - ttxhs 7:0 ttxhs r/w 0x42 start of teletext signal with respect to horizontal sync table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 52 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. offset 0x74 - ttxhl/ttxhd 7:4 ttxhl r/w 0x5 length of ttxrq window; only active at old ttx protocol note: bit ttxo = 1 3:0 ttxhd r/w 0x2 indicates the delay in clock cycles between rising edge of ttxrq output and valid data at pin ttx. offset 0x75 - csynca 7:3 csynca r/w 0x0 advances composite sync against rgb output, adjustable from 0 xtal clocks to 31 xtal clocks 2:0 unused - offset 0x76 - ttxovs 7:0 ttxovs r/w 0x5 first line of occurrence of teletext data in odd field line = (ttxovs + 4) for m-systems line = (ttxove +1) for other systems pal: ttxovs = 0x05 ntsc: ttxovs = 0x06 offset 0x77 - ttxove 7:0 ttxove r/w 0x16 last line of occurrence of teletext data in odd field line = (ttxovs + 3) for m-systems line = ttxove for other systems pal: ttxovs = 0x16 ntsc: ttxovs = 0x10 offset 0x78 - ttxevs 7:0 ttxevs r/w 0x4 first line of occurrence of teletext data in even field line = (ttxovs + 4) for m-systems line = (ttxove + 1) for other systems pal: ttxovs = 0x04 ntsc: ttxovs = 0x05 offset 0x79 - ttxeve 7:0 ttxeve r/w 0x16 last line of occurrence of teletext data in even field line = (ttxovs + 3) for m-systems line = ttxove for other systems pal: ttxovs = 0x16 ntsc: ttxovs = 0x10 offset 0x7a - fal (vertical active size adjustment) 7:0 fal r/w 0x24 defines the video vertical position w.r.t vsync. first active line = fal+4 for m-systems and = fal+1 for other systems. measured in lines, fal = 0 coincides with the first field sync pulse. offset 0x7b - lal (vertical active size adjustment) 7:0 lal r/w 0x29 last active line = lal+3 for m-systems and = fal for other systems. measured in lines, lal = 0 coincides with the first field sync pulse. offset 0x7c - ttxctrl 7 ttx60 r/w 0 0 = enables nabts (fise=1) or european ttx (fise=0). 1 = enables world standard teletext 60hz (fise=1). table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 53 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6 lal8 r/w 1 bit 8 of lal 5 ttxo r/w 0 0 =new ttx protocol selected. at each rising edge of ttxrq a single ttx bit is requested. 1 = old ttx protocol selected. th e encoder provides a window of ttxrq. the length of the window depends on the chosen ttx standard. 4 fal8 r/w 0 bit 8 of fal 3 ttxeve8 r/w 0 bit 8 of ttxeve 2 ttxove8 r/w 0 bit 8 of ttxove 1 ttxevs8 r/w 0 bit 8 of ttxevs 0 ttxovs8 r/w 0 bit 8 of ttxovs offset 0x7d - must be initialized to zero. offset 0x7e - dttxl 7:0 dttxl r/w 0x00 individual lines in both fields (pal counting) can be disabled for insertion of teletext by the respective bits. disabled line =linexx(50hz field rate). bit 7 = line 12; bit 0 = line 5 the mask is only effective if the lines are enabled via ttxovs/ttxove and ttxevs/ttxeve. offset 0x7f - dttxl2 7:0 dttxl r/w 0x00 individual lines in both fields (pal counting) can be disabled for insertion of teletext by the respective bits. disabled line = linexx(50hz field rate) bit 7 = line 20; bit 0 = line 13 the mask is only effective if the lines are enabled via ttxovs/ttxove and ttxevs/ttxeve. offset 0x80 - lcnt_array_line* 7:0 lcnt_array_line r/w - line count array programming data lower 8 bits offset 0x81 - lcnt_array_line* 7:6 unused - 5:0 lcnt_array_line r/w - line count array programming data upper 6 bit offset 0x82 - lcnt_array_adr* 7:4 unused - 3:0 lcnt_array_adr r/w - line count array programming address writing to this address initiates th e transfer of the data previously written into locations 80 and 81 into an internal register array. offset 0x83?0x85 - ltype_array_line* 7:0 ltype_array_line 0x83 -> lsbs 0x85 -> msbs r/w - line type array programming data 2:0 = first index ... 23:21 = last index offset 0x86 - ltype_array_adr* 7:4 unused - table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 54 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3:0 ltype_array_adr r/w - line type array programming address writing to this address initiates th e transfer of the data previously written into locations 83 through 85 into an internal register array. offset 0x87?0x8d - lpatt_array_line* 7:0 lpatt_array_line 0x87 -> lsbs 0x8d -> msbs r/w - line pattern array programming data 13:4 = first duration 3:0 = first select, 2:0 = first value index ... 55:46 = last duration 45 = last select, 44:42 = last value index offset 0x8e - lpatt_array_adr* 7:3 unused - 2:0 ltype_array_adr r/w - line pattern array programming address writing to this address initiates th e transfer of the data previously written into locations 87 through 8d into an internal register array. offset 0x8f - must be initialized to zero. offset 0x90?0x94 - gpio5-gpio1 (0x90=gpio1 ... 0x94=gpio5)* 7 gpio_in_en4 r/w 0 gpio input enable 4 6 gpio_in_en3 r/w 0 gpio input enable 3 5 gpio_in_en2 r/w 0 gpio input enable 2 4 gpio_in_en1 r/w 0 gpio input enable 1 3 oen r/w 1 output enable (active low) 2 status r/w 0 write to register sets the gpio pin if output select is set to 2?b11. read to register returns the status of the gpio pin if gpio_in_en4 is set, otherwise it returns 0. 1:0 out_sel r/w 0 output selection bits 00 = selects gpio_out1 01 = selects gpio_out2 10 = selects gpio_out3 11 = selects gpio_out4. offset 0x95 - vmuxctl 7 8/10-bit r/w 1 0 = 8-bit mode 1 =10-bit mode 6 slice_mode r/w 1 0 = incoming data stream contains a single d1 stream. 1 = incoming data stream is in sliced mode. 5 slice_dir r/w 0 de-slicer control determines where the extracted slice goes. 0: incoming slice 1 == outgoing slice 1 incoming slice 2 == outgoing slice 2 1: incoming slice 1 == outgoing slice 2 incoming slice 2 == outgoing slice 1 table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 55 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4:3 sel r/w 0x0 data slice select mode primary video channel: 00 = slice 1 primary interface 01 = slice 2 primary interface 10 = slice 1 secondary interface 11 = slice 2 secondary interface secondary video channel: 00 = slice 1 secondary interface 01 = slice 2 secondary interface 10 = slice 1 primary interface 11 = slice 2 primary interface 2:0 demux_mode r/w 0x0 output demultiplex mode 000 = yuv422 001 = yuv444 / rgb444 010 = reserved 011 = yuvhd (double interface mode) 100 = yuv422hd (single interface mode) all other modes are reserved. offset 0x96?0x97 - must be initialized to zero. offset 0x98 - value_arr ay_adr/event_type_ptr* 7 unused - 6:4 event_type_ptr r/w - hd sync generator event type pointer; trigger load value 3 unused - 2:0 value_array_adr r/w - value array programming address writing to this address initiates th e transfer of the data previously written into locations 0xbe through 0xc1 into an internal register array. offset 0x99?0x9a - trigger_line* 7:0 trigger_line r/w - this value is used as a line count after trigger. register 0x99 bits 7:0 register 0x9a bits 9:8 offset 0x9b?0x9c - trigger_duration* 7:0 trigger_duration r/w - this value is used as the duration for a certain value after trigger. register 0x9b bits 7:0 register 0x9c bits 9:8 offset 0x9d - trigger_ptr* 7:4 lcnt_ptr_trigger r/w - this value is used as the line count pointer after trigger. 3:2 unused - 1:0 lpatt_ptr_trigger r/w - this value is used as the line pattern pointer after trigger. offset 0x9e - blank_y* 7:0 blank_y r/w 0x90 programmable blank level for the r\y sd-rgb/yuv channel offset 0x9f - blank_uv* 7:0 blank_uv r/w 0 programmable blank level for the uv sd-rgb/yuv channel offset 0xa0 - rgb_ctrl* table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 56 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7:2 unused - 1 demoff r/w 0 yuv to rgb matrix bypass 0 = matrix enabled 1= matrix bypassed 0 reserved - register 0xa1 must be initialized to zero offset 0xa2 - border_y 7:0 border_y r/w 0x80 border color y component for encoder operation mode. this value is r in rgb mode offset 0xa3 - border_u 7:0 border_u r/w 0x80 border color u component for encoder operation mode. this value is g in rgb mode offset 0xa4 - border_v 7:0 border_v r/w 0x80 border color v component for encoder operation mode. this value is b in rgb mode offset 0xa5 - miscctrl 7 unused - 6 m24/30* w 0 parallel video input mode select 0 =30 bit parallel video input mode 1 =24 bit parallel video input mode for details about which pins are used in 24 and 30-bit parallel modes, please refer to section 2 table 5. always reads back ?0?. 5 trigger_mode* r/w 1 external/embedded trigger selection 0 = external vsync/o_e signal triggers the hd-sync generator 1 = d1 embedded o_e signal used to trigger the hd-sync generator. 4 vmode* r/w 1 hd video data path enable 0 = video demultiplexer bypassed for incoming 24/30-bit full parallel video streams (demux_mode settings ignored) 1 = video demultiplexer enabled for hd signals (demux_mode settings apply) 3 unused - 2 sleep r/w 0 video dac sleep mode powers off all analog circuitry but the band gap reference. primary video channel: dac1-4 secondary video channel: dac5-6 1 unused - 0 pd r/w 0 power down mode for dacs; powers all analog circuitry primary video channel: dac1-4 secondary video channel: dac5-6 offset 0xa6 - hdctrl table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 57 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7 y_toco r/w 0 y two?s complement <-> binary offset conversion 0 = data at the output of th e hd-data path are left unchanged 1 = msb of data output of the hd-data path is inverted 6 u_toco r/w 0 u two?s complement <-> binary offset conversion 0 = data at the output of th e hd-data path are left unchanged. 1 = msb of data output of the hd-data path is inverted. 5 v_toco r/w 0 v two?s complement <-> binary offset conversion 0 = data at the output of th e hd-data path are left unchanged. 1 = msb of data output of the hd-data path is inverted. 4 y/r_sync_ins_en r/w 0 enables insertion of r/y sync signals into the component signals. 0 = embedded sync is disabled. 1 = embedded sync is enabled. 3 u/g_sync_ins_en r/w 0 enables insertion of g/u sync signals into the component signals. 0 = embedded sync is disabled. 1 = embedded sync is enabled. 2 v/b_sync_ins_en r/w 0 enables insertion of b/v sync signals into the component signals. 0 = embedded sync is disabled. 1 = embedded sync is enabled. 1 sync_sig_en r/w 0 sync signal insertion enable 0 = no insertion of hd sync module generated sync signals - the external signals are forwarded to the sync ports. 1 = the insertion of hd sync module generated h-sync, v-sync and blank signals is enabled. (note: this disables external sync signals.) h-sync is derived from sync value[0]. v-sync is derived from sync value[1]. c-blank is derived from sync value[2]. 0 upsample_en r/w 0 enable 422 to 444 up-sampling filter 0 = filter switched into bypass mode 1 = filter is active. offset 0xa6 - dac6_adj* 7:5 unused - 4:0 dac6_adj r/w 0 dac6 output level coarse adjustment offset 0xa7 - dac5_adj* 7:5 unused - 4:0 dac5_adj r/w 0 dac5 output level coarse adjustment offset 0xa8 - dacc_adj* 7:4 unused - 3:0 dacc_adj r/w 0 dac5 and 6 output level fine adjustment offset 0xa7 - sync_delay 7 vbiprog 0 0 = programming via vbi disabled (use this mode for 24-bit parallel mode and any other mode cont aining non-656 compliant data). 1 = programming via vbi enabled 6:3 unused - table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 58 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2:0 sync_delay* 1 determines the sync-data delay for the incoming data stream and the associated h/v sync and blank signals. offset 0xa8 - blank_r/y - (hd data path only)* 7:0 blank_r/y 0x0 blank offset for the r/y lsbs offset 0xa9 - blank_g/u - (hd data path only)* 7:0 blank_g/u 0x0 blank offset for the g/u lsbs offset 0xaa - blank_b/v - (hd data path only)* 7:0 blank_b/v 0x0 blank offset for the b/v lsbs offset 0xae - sync_height1* 7:0 sync_height1 - sync raster height bits 7:0 offset 0xaf - sync_height2* 7:0 sync_height2 r/w - sync raster height bits 15:8 offset 0xb0 - sync_width1* 7:0 sync_width1 r/w - sync raster width bits 7:0 offset 0xb1 - sync_width2* 7:0 sync_width2 r/w - sync raster width bits 15:8 offset 0xb2 - sync_trigpos_y1* 7:0 sync_trigpos_y1 r/w - y trigger position bits 7:0 offset 0xb3 - sync_trigpos_y2* 7:0 sync_trigpos_y2 r/w - y trigger position bits 15:8 offset 0xb4 - sync_trigpos_x1* 7:0 sync_trigpos_x1 r/w - x trigger position bits 7:0 offset 0xb5 - sync_trigpos_x2* 7:0 sync_trigpos_x2 r/w - x trigger position bits 15:8 offset 0xb6 - sig1* 7:0 sig1 r - bit 7:0 primary video path signature offset 0xb7 - sig2* 7:0 sig2 r - bit 15:8 primary video path signature offset 0xb8 - sig3* 7:0 sig3 r - bit 7:0 secondary video path signature offset 0xb9 - sig4* 7:0 sig4 r bit 15:8 secondary video path signature offset 0xba - sigctrl* 7:4 sync_ctrl r/w 0x7 number of syncs needed to trigger signature analysis [-1] 3 sig_done r - and combination of signature done for primary and secondary channel 2 sig_enable r/w 0 signature analyzer enable signal 0 = signature analyzer disabled 1 = signature analyzer enabled table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 59 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 1:0 sig_select r/w 0x0 video channel select for signature analysis 00 = video dac 1 and video dac 5 01 = video dac 2 and video dac 5 10 = video dac 3 and video dac 6 11 = video dac 4 and video dac 6 offset 0xbc - blank_msbs* 7:6 unused - 5:4 blank_r/y r/w - blank offset for the hd-r/y channel msbs 3:2 blank_g/u r/w - blank offset for the hd-g/u channel msbs 1:0 blank_b/v r/w - blank offset for the hd-b/v channel msbs offset 0xbe - r/y value_array_line* 7:0 r/y-value_array_line r/w - r/y value array programming data register 0xbe bits 7:0 register 0xc1 bits 9:8 offset 0xbf - g/u value_array_line* 7:0 g/u-value_array_line r/w - g/u value array programming data register 0xbf bits 7:0 register 0xc1 bits 9:8 offset 0xc0 - b/v value_array_line* 7:0 b/v-value_array_line r/w - b/v value array programming data register 0xc0 bits 7:0 register 0xc1 bits 9:8 offset 0xc1 - value_array_line-msbs* 7:6 unused - 5:4 r/y-value_array_line r/w - r/y value array programming data msbs 3:2 g/u-value_array_line r/w - g/u value array programming data msbs 1:0 b/v-value_array_line r/w - b/v value array programming data msbs offset 0xc2 - dac1_adj* 7:5 unused - 4:0 dac1_adj r/w 0 dac1 output level coarse adjustment offset 0xc3 - dac2_adj* 7:5 unused - 4:0 dac2_adj r/w 0 dac2 output level coarse adjustment offset 0xc4 - dac3_adj* 7:5 unused - 4:0 dac3_adj r/w 0 dac3 output level coarse adjustment offset 0xc5 - dac4_adj*. 7:5 unused - 4:0 dac4_adj r/w 0 dac4 output level coarse adjustment offset 0xc6 - dacc_adj* 7:4 unused - 3:0 dacc_adj r/w 0 dac1 to 4 output level fine adjustment table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 60 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.2 audio/clock address space offset 0xc7 - hd_gain_ry(hd data path)* 7:0 hd_gain_r/y r/w 0x00 gain adjust for r/y component in hd-rgb/yuv data path, two?s complement number to adjust the gain from 1-0.5 to 1+-0.5 out=in x (1+ gain/256) offset 0xc8 - hd_gain_gu(hd data path)* 7:0 hd_gain_g/u r/w 0x00 gain adjust for g/u component in hd-rgb/yuv data path, two?s complement number to adjust the gain from 1-0.5 to 1+-0.5 out=in x (1+ gain/256) offset 0xc9 - hd_gain_bv(hd data path)* 7:0 hd_gain_b/v r/w 0x00 gain adjust for b/v component in hd-rgb/yuv data path, two?s complement number to adjust the gain from 1-0.5 to 1+-0.5 out=in x (1+ gain/256) table 29: pnx8510/11 video registers ?continued * indicates not present in secondary video channel bit symbol access value description table 30: pnx8510/11 audio/clock registers bit symbol access value description offset 0000 - clk_audio 7:1 unused - 0 clk_audio r/w 0 0 = i 2 s is in slave mode. 1 = i 2 s is in master mode. offset 0001 - clk_if video interface clock 7:5 unused - 4 clk_if_div8 r/w 0 0 = default (divide by 4). 1 = divide by 8. 3 clk_if_div6 r/w 0 0 = default (divide by 3). 1 = divide by 6. 2:1 clk_if_div r/w 0x0 00 = clk_if is input video clock divide by 1 (feed through). 01 = clk_if is input video clock divide by 2. 10 = clk_if is input video clock divide by 3/6. 11 = clk_if is input video clock divide by 4/8. 0 clk_if_en r/w 0 0 = normal functional mode 1 = set the clock to zero. offset 0002 - clk_proc_div video processing clock 7:5 unused - 4 clk_proc_div8 r/w 0 0 = divide by 4. 1 = divide by 8. 3 clk_proc_div6 r/w 0 0 = default (div.ide by 3). 1 = divide by 6 2:1 clk_proc_div r/w 0x0 00 = clk_proc is input video clock divide by 1 (feed through). 01 = clk_proc is input video clock divide by 2. 10 = clk_proc is input video clock divide by 3/6. 11 = clk_proc is input video clock divide by 4/8.
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 61 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0 clk_proc_en r/w 0 0 = normal functional mode 1 = set the clock to zero. offset 00f4 - i2s_set_reg 7:4 unused - 3:0 i2s_format r/w 0 0000 / philips i 2 s 0001 / lsb justified 16 bits 0010 / lsb justified 18 bits 0011 / lsb justified 20 bits 0100 / msb 1000 / lsb justified 24 bits all other combinations are reserved for future use. offset 00f5(lsbs)?00fb(msbs) - feature_reg 54:47 unused - 46:39 unused - 38:36 unused - 35:33 de-emph_1 r/w 0 de-emphasis enable the digital de-emphasis filter for this channel. 000 = other 001 = 32 khz 010 = 44.1 khz 011 = 48 khz 100 = 96 khz 32 unused - 31 mt1 r/w 0 mute for channel1 and channel2 inside the interpolator 0 = mute off 1 = mute on 30:29 sound_feature r/w 0 controls the mode of the sound processing filters of bass boost and treble. 00 = flat 01 = min 10 = min 11 = max 28:21 master_vol_right r/w 0 master volume control for right channel. two times this 8-bit value to control the volume attenuation. the range is 0 db to ? db in steps of 0.25 db. table 30: pnx8510/11 audio/clock registers ?continued bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 62 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20:17 bboost_right r/w 0 bass-boost for right channel result is dependent on the sound_feature setting [30:29]. 20:17 flat min max 0000 0 db 0 db 0 db 0001 0 db 2 db 2 db 0010 0 db 4 db 4 db 0011 0 db 6 db 6 db 0100 0 db 8 db 8 db 0101 0 db 10 db 10 db 0110 0 db 12 db 12 db 0111 0 db 14 db 14 db 1000 0 db 16 db 16 db 1001 0 db 18 db 18 db 1010 0 db 18 db 20 db 1011 0 db 18 db 22 db 1100 0 db 18 db 24 db 1101 0 db 18 db 24 db 1110 0 db 18 db 24 db 1111 0 db 18 db 24 db 16:15 treble_right r/w 0 treble for right channel. result is dependent on the sound_feature setting [30:29]. 16:15 flat min max 00 0 db 0 db 0 db 01 0 db 2 db 2 db 10 0 db 4 db 4 db 11 0 db 6 db 6 db 14:7 master_vol_left r/w 0 master volume control for left channel. two times this 8-bit value to control the volume attenuation. the range is 0 db to ? db in steps of 0.25 db. 6:3 bboost_left r/w 0 bass-boost for left channel result is dependent on the sound_feature setting [30:29]. (refer to bboost_right [20:17] above.) 2:1 treble_left r/w 0 treble for left channel. result is dependent on the sound_feature setting [30:29]. 16:15 flat min max 00 0 db 0 db 0 db 01 0 db 2 db 2 db 10 0 db 4 db 4 db 11 0 db 6 db 6 db 0 mtm r/w 0 final master mute for the whole interpolator 0 = mute off 1 = mute on offset 00fc - interplator_reg1 7 sdet_on r/w 0 silence detect enable 0 = silence detection circuit disabled 1 = silence detection circuit enabled table 30: pnx8510/11 audio/clock registers ?continued bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 63 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6 silence_override r/w 0 silence override 0 = no override. audio dac silence switch setting depends on the silence detector circuit and or on the master_mute status. 1 = override. the audio dac silence switch is activated. 5 filter_comp r/w 0 switch between ?flat? (for the digital amplifier) or ?compensate? correction filter curve (for the audio dac). 0 = curve for audio dac 1 = curve for digital power amp 4 da_pol_inv r/w 0 select the polarity of the data to the audio dac = a means to control the output signal polarity. the dc and ac dither which must be added to the noise-shaper input will not be inverted when inverting the audio data. 0 = non inverting data out 1 = inverting data out 3:2 sd_value r/w 0 the number of ?zero? samples co unted before the silence detector signals whether there has been digital silence: 00 = 3200 samples 01 = 4800 samples 10 = 9600 samples 11 = 19200 samples 1 unused - 0 unused - offset 00fd - interpolator_reg2 7:6 unused - 5:4 unused - 3 quickmute r/w 0 this is an overriding quickmute on the master channel which mutes the interpolator output si gnal in 32 samples, using the cosine roll-off coefficients.th is overrides the soft mute. 0 = quick mute is off 1 = quick mute on 2 mutemode r/w 0 mute function via micro controller interface: 0 = soft mute mode which takes 32x32 samples to mute 1 = quick mute mode 1 unused - 0 unused - offset 00fe - audio dac power on 7:1 unused - 0 pon r/w 0 1 = power on for audio dac 0 = power off for audio dac table 30: pnx8510/11 audio/clock registers ?continued bit symbol access value description
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 64 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. video programming examples ta bl e 31 to ta b l e 44 provide programming examples for setting up a video channel into pal, ntsc and secam modes. [pnx8510/11_video] has to be substituted with the appropriate i 2 c base address for the primary or secondary video channel. [pnx8510/11_audio] has to be substituted with the appropriate i 2 c base address for the primary or secondary audio channel. remark: the rgb and 1080i examples are applicable to the primary video channel. 9.1 ntsc mode (cvbs/yc 27 mh z yuv422 interface mode) table 31: pnx8510/11_video offset value bit 7 of 0x27 0x0 bit 7 of 0x54 0x0 bit 6 of 0x2d 0xe0 0x3a 0x48 bit 7 and 6 of 0x5f 0x0 bit 7 of 0x62 0x0 bit 7 of 0x2c 0x0 bit 7, 6, 5 of 0x6f 0x0 0x95 0x80 0x28 0x25 0x29 0x1c 0x5a 0x88 bit 7 of 0x5d & 0x5b 0x86 bit 7 of 0x5e & 0x5c 0xba bits [5:0] of 0x5d 0x2a bits [5:0] of 0x5e 0x2e bits [5:0] of 0x5f 0x2e 0x61 0x11 0x62 0x45 0x63-0x66 0x21f07c1f 0x6e 0x10 bit 4 of 0x7c & 0x7a 0x000 bit 6 of 0x7c & 0x7b 0x101 bits[2:0] of 0x72 & 0x70 0x102 bits [6:4] of 0x72 & 0x71 0x68c bits [7:5] of 0x6d & 0x6c 0x0fa bits [4:0] 0x6d 0x0
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 65 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.2 pal mode (cvbs/yc 27 mhz yuv422 interface mode) table 32: pnx8510/11_audio offset value 0x01 0x0 0x02 0x0 table 33: pnx8510/11_video offset value bit 7 of 0x27 0x0 bit 7 of 0x54 0x0 bit 6 of 0x2d 0xe0 0x3a 0x48 bit7and 6 of 0x5f 0x0 bit 7 of 0x62 0x0 bit 7 of 0x2c 0x0 bit 7, 6, 5 of 0x6f 0x0 0x95 0x80 0x28 0x21 0x29 0x1d 0x5a 0x0 bit 7 of 0x5d & 0x5b 0x7d bit 7 of 0x5e & 0x5c 0xaf bits [5:0] of 0x5d 0x23 bits [5:0] of 0x5e 0x35 bits [5:0] of 0x5f 0x35 0x61 0x02 0x62 0x2f 0x63-0x66 0x2a098acb 0x6e 0x20 bit 4 of 0x7c & 0x7a 0x1b bit 6 of 0x7c & 0x7b 0x130 bits[2:0] of 0x72 & 0x70 0x160 bits [6:4] of 0x72 & 0x71 0x65a bits [7:5] of 0x6d & 0x6c 0x107 bits [4:0] 0x6d 0x0 table 34: pnx8510/11_audio offset value 0x01 0x0 0x02 0x0
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 66 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3 secam (cvbs/yc 27 mhz yuv422 interface mode) 9.4 ntsc (rgb 27 mhz yuv422 interface mode table 35: pnx8510/11_video offset value bit 7 of 0x27 0x0 bit 7 of 0x54 0x0 bit 6 of 0x2d 0xe0 0x3a 0x48 bit 7 and 6 of 0x5f 0x0 bit 7 of 0x62 0x0 bit 7 of 0x2c 0x0 bit 7, 6, 5 of 0x6f 0x0 0x95 0x80 0x28 0x21 0x29 0x1d 0x5a 0x0 bit 7 of 0x5d & 0x5b 0x6a bit 7 of 0x5e & 0x5c 0x7f bits [5:0] of 0x5d 0x23 bits [5:0] of 0x5e 0x35 bits [5:0] of 0x5f 0x35 0x61 0x0c 0x62 0x2f 0x63-0x66 0x28a33bb2 0x6e 0x10 bit 4 of 0x7c & 0x7a 0x1b bit 6 of 0x7c & 0x7b 0x130 bits[2:0] of 0x72 & 0x70 0x160 bits [6:4] of 0x72 & 0x71 0x65a bits [7:5] of 0x6d & 0x6c 0x107 bits [4:0] 0x6d 0x0 table 36: pnx8510/11_audio offset value 0x01 0x0 0x02 0x0 table 37: pnx8510/11_video offset value 0x27 0x0 0x54 0x0 0x2d 0x00
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 67 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5 pal (rgb 27 mhz yuv422 interface mode 0x3a 0x49 0x2c 0x0 0x6f 0x0 0x95 0x80 0x28 0x1d 0x29 0x25 0x5a 0x88 bit 7 of 0x5d & 0x5b 0x86 bit 7 of 0x5e & 0x5c 0xba bits [5:0] of 0x5d 0x2a bits [5:0] of 0x5e 0x2e bits [5:0] of 0x5f 0x2e 0x61 0x11 0x62 0x45 0x63-0x66 0x21f07c1f 0x6e 0x90 bit 4 of 0x7c & 0x7a 0x000 bit 6 of 0x7c & 0x7b 0x101 bits[2:0] of 0x72 & 0x70 0x102 bits [6:4] of 0x72 & 0x71 0x68c bits [7:5] of 0x6d & 0x6c 0x0fa bits [4:0] 0x6d 0x0 table 38: pnx8510/11_audio offset value 0x01 0x0 0x02 0x0 table 37: pnx8510/11_video ?continued offset value table 39: pnx8510/11_video offset value 0x27 0x0 0x54 0x0 0x2d 0x00 0x3a 0x49 0x2c 0x0 0x6f 0x0 0x95 0x80 0x28 0x1d 0x29 0x21 0x5a 0x0
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 68 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.6 1080i (74.25 mhz tw o interface 422yuv mode) bit 7 of 0x5d & 0x5b 0x7d bit 7 of 0x5e & 0x5c 0xaf bits [5:0] of 0x5d 0x23 bits [5:0] of 0x5e 0x35 bits [5:0] of 0x5f 0x35 0x61 0x02 0x62 0x2f 0x63-0x66 0x2a098acb 0x6e 0xa0 bit 4 of 0x7c & 0x7a 0x1b bit 6 of 0x7c & 0x7b 0x130 bits[2:0] of 0x72 & 0x70 0x160 bits [6:4] of 0x72 & 0x71 0x65a bits [7:5] of 0x6d & 0x6c 0x107 bits [4:0] 0x6d 0x0 table 40: pnx8510/11_audio offset value 0x01 0x0 0x02 0x0 table 39: pnx8510/11_video ?continued offset value table 41: pnx8510/11_video offset value 0x80 0x05 0x81 0x08 0x82 0x00 0x82 0x01 0x80 0x01 0x81 0x10 0x82 0x01 0x82 0x02 0x80 0x0e 0x81 0x18 0x82 0x02 0x82 0x03 0x80 0x19 0x81 0x06 0x82 0x03 0x82 0x04 0x80 0x05
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 69 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x81 0x18 0x82 0x04 0x82 0x05 0x80 0x01 0x81 0x14 0x82 0x05 0x82 0x06 0x80 0x04 0x81 0x08 0x82 0x06 0x82 0x07 0x80 0x01 0x81 0x0c 0x82 0x07 0x82 0x08 0x80 0x0f 0x81 0x18 0x82 0x08 0x82 0x09 0x80 0x19 0x81 0x06 0x82 0x09 0x82 0x0a 0x80 0x05 0x81 0x18 0x82 0x0a 0x82 0x0b 0x80 0x00 0x81 0x00 0x82 0x0b 0x82 0x0c 0x80 0x00 0x81 0x00 0x82 0x0c 0x82 0x0d 0x80 0x00 0x81 0x00 0x82 0x0d 0x82 0x0e 0x80 0x00 0x81 0x00 table 41: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 70 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x82 0x0e 0x82 0x0f 0x83 0x1c 0x84 0x00 0x85 0x00 0x86 0x00 0x86 0x01 0x83 0x14 0x84 0x05 0x85 0x00 0x86 0x01 0x86 0x02 0x83 0x14 0x84 0x03 0x85 0x00 0x86 0x02 0x86 0x03 0x83 0x0c 0x84 0x03 0x85 0x00 0x86 0x03 0x86 0x04 0x83 0x0c 0x84 0x05 0x85 0x00 0x86 0x04 0x86 0x05 0x83 0x2c 0x84 0x00 0x85 0x00 0x86 0x05 0x86 0x06 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x06 0x86 0x07 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x07 table 41: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 71 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x86 0x08 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x08 0x86 0x09 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x09 0x86 0x0a 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x0a 0x86 0x0b 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x0b 0x86 0x0c 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x0c 0x86 0x0d 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x0d 0x86 0x0e 0x87 0xfb 0x88 0xf6 0x89 0xae 0x8a 0x00 0x8b 0x00 0x8c 0x00 0x8d 0x00 0x8e 0x00 0x8e 0x01 0x87 0xf8 table 41: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 72 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x88 0xf6 0x89 0xae 0x8a 0x00 0x8b 0x00 0x8c 0x00 0x8d 0x00 0x8e 0x01 0x8e 0x02 0x87 0xbb 0x88 0x83 0x89 0xfd 0x8a 0x6e 0x8b 0xbf 0x8c 0xef 0x8d 0x0a 0x8e 0x02 0x8e 0x03 0x87 0xb9 0x88 0x82 0x89 0xae 0x8a 0xb0 0x8b 0x57 0x8c 0x00 0x8d 0x00 0x8e 0x03 0x8e 0x04 0x87 0xbb 0x88 0xc3 0x89 0xfe 0x8a 0xbe 0x8b 0xbf 0x8c 0xef 0x8d 0x0a 0x8e 0x04 0x8e 0x05 0xbe 0x00 0xbf 0x9c 0xc0 0x6a 0xc1 0x2f 0x98 0x00 0x98 0x01 table 41: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 73 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0xbe 0x00 0xbf 0x9c 0xc0 0x6a 0xc1 0x2f 0x98 0x01 0x98 0x02 0xbe 0x66 0xbf 0x64 0xc0 0x78 0xc1 0x00 0x98 0x02 0x98 0x03 0xbe 0x33 0xbf 0xd4 0xc0 0xc0 0xc1 0x3a 0x98 0x03 0x98 0x04 0xbe 0x00 0xbf 0x00 0xc0 0x00 0xc1 0x00 0x98 0x04 0x98 0x05 0xbe 0x00 0xbf 0x00 0xc0 0x00 0xc1 0x00 0x98 0x05 0x98 0x06 0xbe 0xf6 0xbf 0x14 0xc0 0x23 0xc1 0x30 0x98 0x06 0x98 0x07 0x99 0x03 0x9a 0x00 0x9c 0x00 0x9b 0x02 0x9d 0x11 table 41: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 74 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.7 720p (74.25 mhz two interface 422yuv mode) 0xae 0x64 0xaf 0x04 0xb0 0x97 0xb1 0x08 0xb4 0x15 0xb5 0x00 0xb2 0x15 0xb3 0x00 table 42: pnx8510/11_audio offset value 0x01 0x0 0x02 0x0 table 41: pnx8510/11_video ?continued offset value table 43: pnx8510/11_video offset value 0x80 0x05 0x81 0x08 0x82 0x00 0x82 0x01 0x80 0x14 0x81 0x0c 0x82 0x01 0x82 0x02 0x80 0x68 0x81 0x05 0x82 0x02 0x82 0x03 0x80 0x68 0x81 0x05 0x82 0x03 0x82 0x04 0x80 0x05 0x81 0x0c 0x82 0x04 0x82 0x05 0x80 0x00 0x81 0x00 0x82 0x05 0x82 0x06
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 75 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x80 0x00 0x81 0x00 0x82 0x06 0x82 0x07 0x80 0x00 0x81 0x00 0x82 0x07 0x82 0x08 0x80 0x00 0x81 0x00 0x82 0x08 0x82 0x09 0x80 0x00 0x81 0x00 0x82 0x09 0x82 0x0a 0x83 0x1c 0x84 0x00 0x85 0x00 0x86 0x00 0x86 0x01 0x83 0x14 0x84 0x00 0x85 0x00 0x86 0x01 0x86 0x02 0x83 0x2c 0x84 0x00 0x85 0x00 0x86 0x02 0x86 0x03 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x03 0x86 0x04 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x04 0x86 0x05 table 43: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 76 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x05 0x86 0x06 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x06 0x86 0x07 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x07 0x86 0x08 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x08 0x86 0x09 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x09 0x86 0x0a 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x0a 0x86 0x0b 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x0b 0x86 0x0c 0x83 0x00 0x84 0x00 0x85 0x00 0x86 0x0c 0x86 0x0d 0x83 0x00 table 43: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 77 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x84 0x00 0x85 0x00 0x86 0x0d 0x86 0x0e 0x87 0x00 0x88 0x00 0x89 0x00 0x8a 0x00 0x8b 0x00 0x8c 0x00 0x8d 0x00 0x8e 0x00 0x8e 0x01 0x87 0xa8 0x88 0x2c 0x89 0x2a 0x8a 0xbb 0x8b 0x45 0x8c 0x00 0x8d 0x00 0x8e 0x01 0x8e 0x02 0x87 0x5b 0x88 0x09 0x89 0xfc 0x8a 0x09 0x8b 0x7f 0x8c 0x6e 0x8d 0x11 0x8e 0x02 0x8e 0x03 0x87 0x79 0x88 0x82 0x89 0x9e 0x8a 0xb0 0x8b 0x45 0x8c 0x00 0x8d 0x00 0x8e 0x03 0x8e 0x04 0x87 0x5b table 43: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 78 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0x88 0xc9 0x89 0xfe 0x8a 0xb9 0x8b 0x7f 0x8c 0x6e 0x8d 0x11 0x8e 0x04 0x8e 0x05 0x87 0x00 0x88 0x00 0x89 0x00 0x8a 0x00 0x8b 0x00 0x8c 0x00 0x8d 0x00 0x8e 0x05 0x8e 0x06 0x87 0x00 0x88 0x00 0x89 0x00 0x8a 0x00 0x8b 0x00 0x8c 0x00 0x8d 0x00 0x8e 0x06 0x8e 0x07 0xbe 0x00 0xbf 0x00 0xc0 0x00 0xc1 0x20 0x98 0x00 0x98 0x01 0xbe 0x00 0xbf 0x00 0xc0 0x00 0xc1 0x20 0x98 0x01 0x98 0x02 0xbe 0xff 0xbf 0x00 0xc0 0x00 table 43: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 79 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 0xc1 0x10 0x98 0x02 0x98 0x03 0xbe 0x56 0xbf 0x00 0xc0 0x00 0xc1 0x30 0x98 0x03 0x98 0x04 0xbe 0x00 0xbf 0x00 0xc0 0x00 0xc1 0x00 0x98 0x04 0x98 0x05 0xbe 0x00 0xbf 0x00 0xc0 0x00 0xc1 0x00 0x98 0x05 0x98 0x06 0xbe 0x00 0xbf 0x00 0xc0 0x00 0xc1 0x00 0x98 0x06 0x98 0x07 0x99 0x03 0x9a 0x00 0x9c 0x00 0x9b 0x02 0x9d 0x11 0xa8 0x80 0xa9 0x00 0xaa 0x00 0xae 0xed 0xaf 0x02 0xb0 0x71 0xb1 0x06 0xb4 0x20 table 43: pnx8510/11_video ?continued offset value
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 80 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. application information 10.1 audio dac from the simplified schematic figure 32 , it can be seen that the output voltage swing depends upon: ? the maximum digital input level at low frequencies ( ) ? the current mirror gain (ideally 12) ? the ratio of the i/v conversion resistan ce (rconv) and the reference resistance (rref) this relationship is: vout(rms) = 12 ? /2 ? rconv/rref ? vref 0xb5 0x70 0xb 0x10 0xb3 0x70 table 44: pnx8510/11_audio offset value 0x01 0x0 0x02 0x0 table 43: pnx8510/11_video ?continued offset value : max. dig. i/p level v6.0: rconv = 247 ? rref = 18000 ? : -5.67 db = 0.521 => vout(rms) = 0.607 vref fig 32. simplified sc hematic of audio dac v dda v ssa v ss v ref v ref r ref v out l out rconv v ss v dda 7 : 12 7 1 : : 12 v dda p-dac n-dac mdb660 vout rms () 12 rconv 1.41rreg --------------------------- vref =
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 81 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. the reference resistor is dimensioned to be 18 k ? . since the reference voltage vref is nominally half the supply voltage, the i/v conversion resistor must be dimensioned by: rconv = vout(rms)/vref ? 2 / (12 ? ) ? rref for an rms output voltage of 1000 mv rms, a reference voltage of 1.65 v, a reference resistance of 18 k ? and a maximum digital input level of 0.521 (-5.67 db), the i/v conversion resistor should be 2470 ? . 10.2 dac reconstruction filter figure 33 shows the circuitry for the reconstructi on filter of the video d/a converters. 10.3 video dacs of primary an d secondary video channels the video dacs used in both the primary and secondary video channels employ segmented current mode architecture. the pr ogramming feature of dacs is valid for both the primary and secondary video channels. the primary video channel has in its path four dacs: r, g, b and cvbs. the programming option ?fine adjust? ? via the common four bits of i 2 c [3:0] ? can simultaneously adjust the central output level of all four dacs in a range of 7% in 1% increments. please note the four bits are signed values. ta bl e 45 shows the programming values. fig 33. dac reconstruction filter mdb661 rv5 75 ? cv3 390 pf l3 2.7 h c40 120 pf cv4 560 pf cvbs2 rca jack rv6 75 ? cv5 390 pf l5 2.7 h l6 2.7 h l4 j6 2.7 h l8 2.7 h c41 120 pf cv6 560 pf luma1 rv7 75 ? cv7 390 pf l7 2.7 h c42 120 pf cv8 560 pf vout6 chroma1_out luma1_out 4 2 765 3 1 j7 s-video
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 82 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. the programming option ?coarse adjust? uses five separate bits [14:10] of i 2 c to independently adjust the output level of each r, g, b and cvbs dac between 0.58 v and 1.23 v (in increments of 21 mv, assuming an effective load of 75 ? / 75 ? = 37.5 ? ). note that these five bits are not signed. table 45: common i 2 c bits for all dac devices (output level: fine adjust ment in 1% increments) bits vout 3210 0000 0% 0001 +1% 0010 +2% 0011 +3% 0100 +4% 0101 +5% 0110 +6% 0111 +7% 1000 0% 1001 -1% 1010 -2% 1011 -3% 1100 -4% 1101 -5% 1110 -6% 1111 -7% table 46: separate i 2 c bits 31x21mv (output level: coarse adjustment for each dac) bits vout 11111 43210 00000 +0% 00001 +3.6% 00010 +7.2% 00011 +10.7% 00100 +14.3% 00101 +17.9% 00110 +21.5% 00111 +25.0% 01000 +28.6% 01001 +32.2% 01010 +35.8% 01011 +39.4% 01100 +42.9% 01101 +46.5%
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 83 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3.1 programming example assuming an effective load of 75 ? / 75 ? = 37.5 ? , rset = 1 k ? , the coarse bits are set to 0 0 0 0 and the fine adjust bits are se t to 0 0 0 0 0. the out put will be sitting at the minimum level of vout = 0.579 v. for example, if vout is set to 1 v, then the fine adjust bits should be set to 0 0 0 0 0 and the coarse adjust bits set to 1 0 1 0 0. figure 34 provides an example for calculating the rset for the video dacs from given output voltage and termination. 01110 +50.1% 01111 +53.7% 10000 +57.3% 10001 +60.8% 10010 +64.4% 10011 +68% 10100 +71.6% 10101 +75.1% 10110 +78.7% 10111 +82.3% 11000 +85.9% 11001 +89.5% 11010 +93.0% 11011 +96.6% 11100 +100.2% 11101 +103.8% 11110 +107.4% 11111 +110.9% table 46: separate i 2 c bits 31x21mv ?continued (output level: coarse adjustment for each dac) bits vout 11111 43210
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 84 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.3.2 sleep and power down modes sleep mode occurs when all current output switches are disabled asynchronously so that no current flows in eit her iout or idump pins i.e., iout = idump = 0. sleep mode allows a rapid recovery from a low power consumption state. each dac can be put into sleep mode asynchronously where io ut = idump = 0, yet still supply current flows to power the bandgap, opmap, and other analog dac components, including the digital logic. powerdown mode occurs when each dac can be asynchronously put into zero state current so that all current ou tput switches are disabled. th is includes current to all analog and digital components of the dac such as bandgap reference, opmaps, etc. in this mode iddd = idda = 0. 10.4 device initialization the pnx8510/11 must be synchronously reset by providing a video clock to both clock inputs (dv_clk1 and dv_clk2) before the reset line (reset_n) is pulled high. this will ensure correct in itialization. failure to follo w this sequence may result in no video output from the pnx8510/11, or similar symptoms. the i 2 c bus of the pnx8510/11 is disabled during the reset of the device and the i2c_sda pin is only released after the reset sequence is complete. this release requires that an audio clock is applied to the i2s_aos1_clk, in addition to the video clock applied to dv_clk1. therefore, even in applications which do not make use of the audio functionality of th e pnx8510/11, it is still nece ssary to apply a clock to i2s_aos1_clk. rssetnom = 1 k ? for rl = 37.5 ? (double termination) rsetmax = 2 k ? for rl = 75 ? icompn = reference currents for up to 6 dacs. iout + idump = 1023i1 = constant, idump = (1023 - d) i1, vdump = iout x rl, vout = iout x rl. voutmin = 15.57 ma x 37.5 ? = 0.584 v (full-scale, fine adjust = 0%) voutmin = 32.80 ma x 37.5 ? = 1230 v (full-scale, fine adjust = 0%) fig 34. video channel dac programming mdb66 2 6 pcomp pcomp icomp1 dac10 comp v ssa v ssa v ssa v ssa r o = 2 x 75 ? r l = r o / 2 r dump = 0.1 or 2 ? separate output level coarse adjust for each dac i ref m = ? 7 to + 7 4-bit fine adjust n = 0 to 31 5-bit coarse adjust d = 0 to 1023 10-bit digital inputs 10-bit current dac with programmable output level adjustments of fine and coarse iout idump iout vbg rs ------------ - 16.4 100 ---------- ?? ?? 1 100 m + 100 -------------------- ?? ?? m 100 -------- - ? + 28 n + 23 16 ----------------- - d = i1 lsbcurrent = ?? ?? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 85 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. limiting values 12. characteristics table 47: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd(adac) digital supply audio 3.15 3.45 v v dd(vdac) digital supply video 3.15 3.45 v v dda(vdac) analog supply video 3.15 3.45 v v dda(adac) analog supply audio 3.15 3.45 v vil low level input voltage -0.5 0.8 v vih high level input voltage 2.0 - v ili input leakage current - 1 ua vil low level input voltage -0.5 0.3 v dd(i 2 c) v vih high level input voltage 0.7 v dd(i 2 c) v dd(i 2 c) +0.3 v table 48: electrical characteristics range: vdd = 3.0 to 3.6 v; tamb = 0 to +70 c. in the following table vdd = 3.3; tamb = 25 c, unless otherwise stated symbol parameter conditions min typical max unit power consumption sd rgb/y-c 1.02 1.15 w half hd yprpb 1.09 1.26 w full hd yprpb 1.58 1.97 w supply v dd(adac) digital supply audio 3.15 3.3 3.45 v v dd(vdac) digital supply video 3.15 3.3 3.45 v v dda(vdac) analog supply video 3.15 3.3 3.45 v v dda(adac) analog supply audio 3.15 3.3 3.45 v inputs vil low level input voltage -0.5 0.8 v vih high level input voltage 2.0 v ili input leakage current - 1 ua ci input capacitance clocks 10 pf data 8 pf i/os at high impedance 8 pf outputs vol low level output voltage iol=2ma - 0.4 v voh high level output voltage ioh=2ma 2.4 - v i 2 s bus: sda, scl vil low level input voltage -0.5 0.3v dd(i 2 c) v vih high level input voltage 0.7v dd(i 2 c) v dd(i 2 c) +0.3 v
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 86 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. vol low level output voltage (sda) iol=3ma - 0.4 v io output current during ack 3 - ma input timing tsu input data setup time 0 ns thd input data hold time 4.5 ns data and reference signal output timing gpios are for static use only. hsync out and vsync out are aligned to the analog video data. audio dac outputs v out full scale output voltage [1] 1.0 v rms v com common mode output voltage [2] 1.65 v r load load resistance 4 k ? r out , v ref equivalent ac resistance seen at vref terminal 25 k ? s/(thd+n) (thd+n)/s @ 0db, 1 khz 88 92 db s/n snr at digital silence 95 db(a) dc offset characteristics v offset dc-offset compensation -43 mv video dac outputs inl integral nonlinearity static 0.6 lsb dn 0.5 lsb t r output rise time load 37.5 ? //15pf 2.3 ns t f output fall time load 37.5 ? //15pf 2.3 ns f clk clock frequency 100 mhz i out output current programming see section 10 for application information. v ref 1.23 v t det detection threshold (comparator) 100 ns t dos operating to sleep delay 200 ns t dop operating to power down delay 200 ns t dsp sleep to power down delay 200 ns t dso sleep to operating 200 ns t dpo power down to operating delay 200 ns t dps power down to sleep delay 200 ns table 48: electrical characteristics ?continued range: vdd = 3.0 to 3.6 v; tamb = 0 to +70 c. in the following table vdd = 3.3; tamb = 25 c, unless otherwise stated symbol parameter conditions min typical max unit
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 87 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] full scale output voltage is directly propor tional to dc voltage at vref pin (vdda/ 2) and maximum digital signal level at lo w frequencies. relation: vout(rms) = * 1.645 * vref/1.41, = maximum digital input level at low frequencies. [2] common mode output voltage equals vref=vdda/2/ 13. package outline fig 35. htqfp package outline. unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot638-1 01-03-30 03-04-07 d (1) e (1) 14.1 13.9 16.15 15.85 d h e h 7.1 6.1 7.1 6.1 1.15 0.85 b p b p e e a 1 a l p detail x l (a 3 ) b 25 h d h e a 2 v m b d z d a c z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 10 mm scale htqfp100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad sot638-1 d h e h exposed die pad side
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 88 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. soldering 14.1 introduction to solder ing surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow solder ing is recommended. in these situations reflow soldering is recommended. 14.2 reflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed- circuit board by scree n printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 220 c (snpb process) or below 245 c (pb-free process) ? for all bga and ssop-t packages ? for packages with a thickness ? 2.5 mm ? for packages with a thickness < 2.5 mm and a volume 350 mm 3 so called thick/large packages. ? below 235 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indica ted on packing, must be respected at all times. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following co nditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 89 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): ? larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; ? smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-ci rcuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, t he package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will e liminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 14.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your ph ilips semiconductors sales office. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 49: suitability of surface mount ic packages for wave and reflow soldering methods package [1] soldering method wave reflow [2] bga, lbga, lfbga, sqfp, ssop-t [3] , tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable pmfp [8] not suitable not suitable
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 90 of 92 9397 750 12612 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one so ldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circ uit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] hot bar or manual soldering is suitable for pmfp packages. 15. revision history table 50: revision history rev date cpcn description 04 20040112 upgraded to product data (9397 750 12612) modifcations to: ? section 7.6 : remark amended ? section 10.4 : added 03 20030926 preliminary data (9397 750 09223). major updates to docs by hari tadepalli of vlsi ic engineering as requested format upgrade to dvp template. more detail added to: luminance and chrominance processing, macrovision? and programming interface. 02 20011008 853-2300 27221 supersedes initial version of 27 august 2001 (9397 750 08495). the format of this document has been redesigned to comply with philips semiconductors? new presentation and information standard. 01 20010827 preliminary release posted on bhs (dvi) intranet web site
philips semiconductors pnx8510/11 analog companion chip product data rev. 04 ? 12 january 2004 91 of 92 9397 750 12612 ? philips electronics n.v. 2004 all rights reserved. 16. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semicondu ctors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status 17. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. disclaimers life support ? these products are not desi gned for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status ?production?), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 19. licenses 20. trademarks nexperia ? is a trademark of koninklijke philips electronics n.v. macrovision ? is a trademark of the macrovision corperation 21. contact information for additional information, please visit http://www.semiconductors.philips.com. for sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com. level data sheet status [1] product status [2] [3] definition i objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. ii preliminary data qualification this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product specif ication. philips semiconductors reserves the right to make changes at any time in order to improve the des ign, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips? i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by phili ps. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004. printed in netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher fo r any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 12 january 2004 document order number: 9397 750 12612 contents philips semiconductors pnx8510/11 analog companion chip 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 pnx8510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 pnx8511 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 video pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 video modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.2 video input modes . . . . . . . . . . . . . . . . . . . . . 10 7.1.3 video input module . . . . . . . . . . . . . . . . . . . . . 12 7.1.4 video dac control . . . . . . . . . . . . . . . . . . . . . 14 7.1.5 vbi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1.6 primary video channel . . . . . . . . . . . . . . . . . . 17 7.1.7 secondary video channel . . . . . . . . . . . . . . . . 17 7.1.8 pal/ntsc/secam encoder. . . . . . . . . . . . . . 18 7.1.9 luminance and chrominance processing . . . 19 7.1.10 sync generator . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1.11 macrovision? - pnx8510 . . . . . . . . . . . . . . . 23 7.2 hd data path . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2.1 hd-sync generator module. . . . . . . . . . . . . . . 24 7.2.2 trigger generation. . . . . . . . . . . . . . . . . . . . . . 26 7.2.3 signature analysis . . . . . . . . . . . . . . . . . . . . . 30 7.2.4 limitations of the video pipe . . . . . . . . . . . . . . 31 7.3 audio pipeline . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.3.1 audio interface operation . . . . . . . . . . . . . . . . 32 7.3.2 mute modes . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4 programming interface . . . . . . . . . . . . . . . . . . 34 7.5 gpio block . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.6 clock module . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.6.1 clocks video submodule. . . . . . . . . . . . . . . . . 38 7.6.2 clocks audio submodule. . . . . . . . . . . . . . . . . 38 7.7 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 register descriptions . . . . . . . . . . . . . . . . . . . 40 8.1 video address space . . . . . . . . . . . . . . . . . . . 44 8.2 audio/clock address space . . . . . . . . . . . . . . 60 9 video programming examples . . . . . . . . . . . . 64 9.1 ntsc mode (cvbs/yc 27 mhz yuv422 interface mode). . . . . . . . . . . . . . . . . . . . . . . . 64 9.2 pal mode (cvbs/yc 27 mhz yuv422 interface mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10 application information. . . . . . . . . . . . . . . . . . 80 10.1 audio dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.2 dac reconstruction filter . . . . . . . . . . . . . . . . . 81 10.3 video dacs of primary and secondary video channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.3.1 programming example . . . . . . . . . . . . . . . . . . 83 10.3.2 sleep and power down modes. . . . . . . . . . . . 84 10.4 device initialization. . . . . . . . . . . . . . . . . . . . . 84 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 85 12 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 85 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 87 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.2 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 88 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 88 14.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 89 14.5 package related soldering information. . . . . . 89 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 90 16 data sheet status . . . . . . . . . . . . . . . . . . . . . . 91 17 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 19 licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 20 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 21 contact information . . . . . . . . . . . . . . . . . . . . 91

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